Texas Instruments specifications Sdram interface TNETX3270 Terminal Interface to SDRAMs

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

SDRAM interface (continued)

Table 15. TNETX3270 Terminal Interface to SDRAMs

TERMINALS

SDRAM TERMINAL FUNCTION

 

 

TNETX3270

SDRAM

 

 

 

 

DA13

A13

Row/bank address (64-M SDRAMs only)

 

 

 

DA12

A12

Row/bank address (64-M SDRAMs only)

 

 

 

DA11

A11

Row/bank address

 

 

 

DA10

A10

Row address/auto-precharge select

 

 

 

DA09

A9

Row address

 

 

 

DA08

A8

Row address/column address (8 only)

 

 

 

DA07

A7

Row address/column address

 

 

 

DA06

A6

Row address/column address

 

 

 

DA05

A5

Row address/column address

 

 

 

DA04

A4

Row address/column address

 

 

 

DA03

A3

Row address/column address

 

 

 

DA02

A2

Row address/column address

 

 

 

DA01

A1

Row address/column address

 

 

 

DA00

A0

Row address/column address

 

 

 

DRAS

RAS

Row address strobe

 

 

 

DCAS

CAS

Column address strobe

 

 

 

DW

W

Write enable

 

 

 

DCLK

CLK

Clock

 

 

 

DD31±DD16

DQ15±DQ0

SDRAM1. Data I/O (16 SDRAMs)

 

 

 

DD15±DD00

DQ15±DQ0

SDRAM0

 

 

 

DD31±DD24

DQ7±DQ0

SDRAM3. Data I/O (8 SDRAMs)

 

 

 

DD23±DD16

DQ7±DQ0

SDRAM2

 

 

 

DD15±DD08

DQ7±DQ0

SDRAM1

 

 

 

DD07±DD00

DQ7±DQ0

SDRAM0

 

 

 

DA13 and DA12 should be left unconnected if 16M-bit SDRAMs are used. The remaining functional SDRAM terminals that are not directly controlled by the SDRAM interface should be tied off from the external system during operation (see Table 16).

Table 16. SDRAM Terminals Not Driven by the TNETX3270

HELD

SDRAM

SDRAM

TERMINAL

TERMINAL FUNCTION

 

 

 

 

Low

CS

Chip select

 

 

 

High

CKE

CLK enable

 

 

 

Low

DQM

Data mask (8 SDRAMs)

 

 

 

Low

DQML

Data mask (16 SDRAMs)

 

 

 

Low

DQMU

Data mask (16 SDRAMs)

 

 

 

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice