Texas Instruments TNETX3270 specifications Frame format on the NM port

Page 20

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

frame format on the NM port

The frame format on the NM port differs slightly from a standard Ethernet frame format. The key differences are: the frame always contains an IEEE Std 802.1Q header in the four bytes following the source address (see Figure 2). The TPID (tag protocol identifier or ethertype) field, however, is used in the switch for other purposes, so a frame transmitted out of the switch on the NM port does not have the IEEE Std 802.1Q TPID of 81±00 (ethertype constant) value in these two bytes.

The first TPID byte output contains:

DThe frame source port number in the least significant bits. This allows the frame source port number to be carried within the frame, which is useful for processing BPDUs, for example.

DA cyclic redundancy check (CRC) type indicator (crctype) in the most significant bit (bit 7).

•If crctype = 1, then the CRC word in the frame excludes the IEEE Std 802.1Q header.

•If crctype = 0, then the CRC word in the frame includes the IEEE Std 802.1Q header. This CRC word is for a regular IEEE Std 802.1Q frame format with the value in the IEEE Std 802.1Q TPID of 81±00 (ethertype constant) in the TPID field. Because the internal frame format uses the TPID field for other purposes in the manner being described, it is necessary to insert the IEEE Std 802.1Q TPID of 81±00 (ethertype constant) value into the TPID field if the frame needs to be restored to a normal IEEE Std 802.1Q frame format, which passes a CRC check.

To provide a CRC word, which includes the header, the NM port generates a new CRC word as the frame is being read out. It simultaneously checks the existing CRC in the frame and, if an error is found, ensures that the final byte of the newly generated CRC is corrupted to contain an error, too. The CRC word is deliberately corrupted if the header parity protection (described in the following) indicates an error in the header. In either case, the pfe bit also is set to 1 after the final byte of the frame has been read from NMdata.

If the frame was received on a port other than the NM port, then the crctype bit is set if an IEEE Std 802.1Q tag header was inserted into the frame during ingress.

•If crctype = 1, a header was inserted.

•If crctype = 0, a header was not inserted (crctype also is 0 if the frame VLAN ID was 0x000 and was replaced by the port VLANID (PVID) from the PortxQtag register).

In an IEEE Std 802.1D-compliant application, the header simply can be removed from the frame to produce a headerless frame with a correct CRC word.

•All other bits in the byte are reserved and are 0. The second TPID byte output contains:

DOdd-parity protection bits for the other three bytes in the tag header

DBit 5 protects the first byte of the TPID field (i.e., the one containing crctype and source port number).

DBit 6 protects the first byte of the VLAN ID field.

DBit 7 protects the second byte of the VLAN ID field.

DAll other bits in the byte are reserved and are 0.

20

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Page 19 Page 21
Image 20
Page 19 Page 21
Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
Top Page Image Contents