Texas Instruments TNETX3270 DIO/DMA interface, DIO/DMA write cycle, SDATA7± Z SDATA0

Page 58

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

DIO/DMA interface

The DIO interface is asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces.

DIO/DMA write cycle

timing requirements (see Figure 18)

NO.

MIN MAX

UNIT

1

tw(SCSL)

Pulse duration,

low

24

ns

SCS

2

tw(SCSH)

Pulse duration,

high

12

ns

SCS

3

tsu(SRNW)

Setup time,

low before

↓

0

ns

SRNW

SCS

4

tsu(SAD)

Setup time, SAD1±SAD0 and

valid before

↓

0

ns

SDMA

SCS

5

tsu(SDATA)

Setup time, SDATA7±SDATA0 valid before

↓

0

ns

SCS

operating characteristics over recommended operating conditions (see Figure 18)

NO.

PARAMETER

MIN

MAX

UNIT

6

tw(SRDYH)

Pulse duration,

high

12

ns

SRDY

7

td(SRNW)

Delay time, from

↓ to

↑

0

ns

SRDY

SRNW

8

td(SAD)

Delay time, from

↓ to SAD1±SAD0 and

invalid

0

ns

SRDY

SDMA

9

td(SDATA)

Delay time, from

↓ to SDATA7±SDATA0 invalid

0

ns

SRDY

10

td(SCS)

Delay time, from

↓ to

↑

0

ns

SRDY

SCS

11

td(SRDY)1

Delay time, from

↓ to

↑

0

ns

SCS

SRDY

12

t

Delay time, from

↓ to

↓²

0

ns

SCS

SRDY

d(SRDY)2

13

td(SRDY)3

Delay time, from

↑ to

↑

0

24

ns

SCS

SRDY

²When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25±100 ms) between SCS being asserted and SRDY being asserted.

5		12
4		1	2
3	11	10	13

SCS (input)

7

SRNW (input)

8

SAD1±SAD0,

SDMA (inputs)

	9
SDATA7± Z	Z
SDATA0
(inputs)	6
	6
SRDY	Z
SRDY
(output)

Figure 18. DIO/DMA Write Cycle

58	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 58

Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice