Texas Instruments TNETX3270 10-/100-Mbit/s MAC interface, 10-/100-Mbit/sreceive ports 24, 25

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

		1
THxCLK
(input)
	2	2
THxSYNC
(input)
THxCOL	3	5
THxCRS
THxLINK
THxRXD3±THxRXD0
THxRXDV		4	6
(inputs)		4	6
THxTXEN	7		8
THxTXEN
THxTXD3±THxTXD0
THxRENEG
(outputs)

Figure 13. 10-Mbit/s Interface (Ports 00±23)

10-/100-Mbit/s MAC interface

Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the TNETE2101 devices.

10-/100-Mbit/sreceive ports (24, 25, 26)

timing requirements (see Note 7 and Figure 14)

NO.			MIN	MAX	UNIT
1	tc(MxxRCLK)	Cycle time, MxxRCLK	25	25	ns
2	tw(MxxRCLKL)	Pulse duration, MxxRCLK low			ns
3	tw(MxxRCLKH)	Pulse duration, MxxRCLK high	14		ns
4²	t	Setup time, MxxRXD3±MxxRXD0 valid before MxxRCLK↑	5		ns
	su(MxxRXD)
4²	t	Setup time, MxxRXDV valid before MxxRCLK↑	5		ns
	su(MxxRXDV)
4²	t	Setup time, MxxRXER valid before MxxRCLK↑	5		ns
	su(MxxRXER)
5²	t	Hold time, MxxRXD3±MxxRXD0 valid after MxxRCLK↑	5		ns
	h(MxxRXD)
5²	t	Hold time, MxxRXDV valid after MxxRCLK↑	5		ns
	h(MxxRXDV)
5²	t	Hold time, MxxRXER valid after MxxRCLK↑	5		ns
	h(MxxRXER)

² xx = ports 24, 25, and 26

NOTE 7: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxRXD3±MxxRXD0 is driven by the PHY on the falling edge of

MxxRCLK. MxxRXD3±MxxRXD0 timing must be met during clock periods when MxxRXDV is asserted. MxxRXDV is asserted and deasserted by the PHY on the falling edge of MxxRCLK. MxxRXER is driven by the PHY on the falling edge of MxxRCLK.

	1
4	5
2	2
MxxRCLK
(input)

MxxRXD3±MxxRXD0

MxxRXDV

MxxRXER

(inputs)

Figure 14. 10-/100-Mbit/s Receive Ports

54	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 54

Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice