Texas Instruments TNETX3270 Ieee Std 802.1Q headers ± reception, Address maintenance

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

IEEE Std 802.1Q headers ± reception

When the internal address-lookup engine (IALE) examines the received frame, it contains an IEEE Std 802.1Q header (after the source address). The header used depends on the port configuration. If the port is configured as an access port, then IALE always uses the default VLAN ID (VID) programmed for this port. It accepts all received frames on this port as untagged. If the frame already contains a header, it is tagged again. If the port is programmed as a non-access port, then the header added depends on the received frame. If the frame is not tagged, or the value of the header field is 0x000, then the default port VID is used to tag the frame internally. Otherwise, the VID contained in the frame is used by the IALE.

The IALE does not support all 4096 VLAN IDs that can be encoded within the IEEE Std 802.1Q header at the same time. The TNETX3270 has support for 32 VLANs, the VID in the received frame is compared with these 32 VLAN IDs to see which (if any) it matches. The designer can use any of the 4096 VLAN ID values for these 32 VLAN IDs.

unknown VLAN

If there is no match, then the rest of the address-lookup process is abandoned. A new VLAN interrupt is provided to the attached CPU. The source address, VLAN ID, and port information is provided in internal registers so that the CPU can determine if it wants to add this VID to the lookup table. If the destination address is unicast, then the frame is discarded. If the destination address is multicast/broadcast, then the frame is forwarded based on a programmable port mask.

known VLAN

If there is a match, the VLAN index associated with this VID together with the destination and source address, are forwarded to the address-lookup and subsequent routing process. Only one of the VLAN IDs match if they have been programmed correctly. If more than one matches, the hardware chooses one of them.

new VLAN member

The IALE checks to see if the source port already has been declared as a member of this VLAN. If not, then an interrupt is provided to allow the attached CPU to add this port as a new member of the VLAN.

IEEE Std 802.1Q headers ± transmission

The IEEE Std 802.1Q header is carried in the frame to the transmitting MAC port, where the decision to strip out the header before transmission is made, based on the port configuration. If the port is configured as an access port, the header is stripped before transmission. If the frame is only 64 bytes long, then 4 bytes of pad (0s) are inserted between the end of the data and the start of the CRC word (a new CRC value is calculated and inserted in the frame). If the port is configured as a non-access port, the VID is compared with the default port VID. If they match, the header is stripped. Otherwise, the header is retained.

If the frame is transmitted to the NM port, then no header stripping occurs. The frame is transmitted unaltered. It may contain one or two headers, depending on how the frame was originally received.

address maintenance

The addresses within the IALE can be maintained automatically by the TNETX3270, where addresses are learned/updated from the wire and deleted, using one of two aging algorithms. Multicast addresses are not automatically learned or aged. The attached CPU can add/update, find, or delete address records via the DIO interface.

At times of peak activity, it may not be possible to learn or update every source address that is received. The IALE backlogs up to one source address per port under these circumstances. Subsequent source addresses received on a backlogged port are not learned/updated until that port's backlog has been cleared. Lookups are always given priority in the IALE, so these can never backlog.

The learning and aging processes are independent. This allows addresses to be learned automatically from the wire, but allows the CPU to manage the aging process under software control.

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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