Texas Instruments TNETX3270 Collision-based flow control, Ieee Std 802.3 flow control

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

collision-based flow control

Collision-based flow control provides a means of preventing frame reception for ports that are operating in half-duplex mode. While the number of free buffers is fewer than the specified threshold, ports in this state that are not currently transmitting generate collisions when they start to receive a frame. The jam sequence transmitted (55.55.55.55.55.55.55.5D.DD.DD.DD.DD (hex) starts approximately when the source address starts to receive. Port 8 begins jam sequence after approximately eight bytes of payload data (i.e., after the source address) have been received.

These forced collisions are not limited to a maximum of 16 consecutive collisions, and are independent of the normal backoff algorithm.

IEEE Std 802.3 flow control

IEEE Std 802.3X flow control provides a means of reducing network congestion on ports that are operating in full duplex mode, via special pause frames. It is symmetrical, so that devices that transmit pause frames also must respond to received pause frames.

Pause frames and their behavior are fully described in the IEEE Std 802.3X standard, but in essence they comprise:

D48-bit multicast destination address 01.80.C2.00.00.01

D48-bit source address ± is read from the Devnode register when transmitted by this device.

D16-bit length/type field, containing the value 88.08

D16-bit pause opcode equal to 00.01

D16-bit pausetime. This specifies a nonzero number of pausequanta. A pausequantum is 512 bit times.

DPadding as required/desired

D32-bit frame-check sequence (CRC word)

All quantities above are hexadecimal and are transmitted most significant byte first. Within the byte they are transmitted least significant bit first.

The padding is required to fill out the frame to a minimum of 64 bytes. The standard allows pause frames longer than 64 bytes to be discarded or interpreted as valid pause frames. This device recognizes any pause frame that is between 64 bytes and 1531 bytes long. It always transmits 64-byte pause frames.

Each 10-/100-Mbit/s port can request IEEE Std 802.3X pause-frame support via the reqnp (= 0) bit within its Portxcontrol register. The 100-/1000-Mbit/s port has independent control for transmission and reception of IEEE Std 802.3X pause frames, and can request IEEE Std 802.3X flow control via the reqntxp (= 0) and reqnrxp (= 0) bits within its Portxcontrol.

Outgoing pause frames are issued only when:

Dpause (10/100) = 1

DThe port is operating in the full-duplex mode.

Dflow = 1 in Syscontrol

Incoming pause frames are acted on only when:

Dpause = 1 or pausetx = 1 (i.e., incoming pause frames are recognized in both full-duplex and half-duplex modes, regardless of the value of the flow bit)

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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