Texas Instruments TNETX3270 specifications Frame routing, Vlan support, Iale

Page 39

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

frame routing

VLAN support

The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 8 and described in the following paragraphs.

 

Receive

 

 

 

 

Record

 

 

 

 

IEEE Std

 

 

 

 

 

 

 

 

 

 

 

Non-

 

 

 

 

Number

 

 

 

 

802.1Q

 

 

 

VLAN

ADDR

 

 

 

 

IEEE Std

Reset to

Port Information

 

 

 

Format

VLAN and

Port Numbers,

 

 

 

 

802.1Q

All 0s

 

 

 

Frame

 

 

 

Reset is

 

 

 

Format

 

 

Ethernet

Time Stamps

 

 

Header

 

 

 

 

Don't Care

 

 

Frame

 

 

Addresses

Locked, Secure,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NBLCK, New

 

 

If rxacc = 1

Header

 

 

 

 

Source

 

 

 

 

Header Inserted

Possibly

 

Source Address (SA)

and

 

 

 

 

If VLAN ID = 0x000

Inserted

Header

Destination Address (DA)

Destination

No

Port

 

 

 

 

 

 

Lookups

 

 

VLAN ID Replaced

 

 

Inserted

 

 

 

 

Match

Information

 

Reset 0x0001

 

 

 

 

 

 

 

SA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Source Port's

Inserted

 

 

 

VLANnQID

VLAN

DA

 

 

 

 

Header

 

 

 

VLAN

 

 

 

 

 

 

PortxQtag

VLAN ID

 

VLAN ID

 

 

Unicast/

 

 

 

 

 

 

Index

 

 

 

 

 

 

 

 

 

Frame-Routing

 

Nauto

 

 

 

 

 

Lookup

 

 

 

Multicast

 

 

 

 

 

 

 

 

 

 

 

Algorithm

 

UnkVLAN

 

 

 

 

 

 

Reset

 

 

 

UnkUniPorts

 

 

 

 

 

 

 

 

 

 

UnkMultiPorts

 

 

 

 

 

Queue

 

 

1st Location:

No Match

 

 

 

Lshare

 

 

 

 

 

 

 

UnkSrcPorts

 

 

 

 

Manager

 

0x001

 

 

 

 

 

SysControl

 

 

 

 

 

 

UnkVLANPort

 

Nage

 

 

 

 

 

All Others:

 

 

 

 

 

 

 

 

 

 

 

 

TxBlockPorts

 

 

 

 

 

 

 

 

0x000

 

 

 

RxUniBlockPorts

Mirror

 

 

 

RAM

 

 

Source Port Number

 

 

RxMultiBlockPorts

 

 

 

 

 

 

 

 

 

 

MirrorPort

 

 

 

 

 

 

 

 

Port Routing Code

 

 

UplinkPort

 

 

 

 

 

 

 

 

 

 

TrunkMapx

 

Disable

All Ports

 

 

 

 

 

 

 

 

 

TrunkxPorts

 

 

 

 

 

 

 

 

 

 

 

 

Portxcontrol

 

 

Queue

 

 

 

 

 

 

NLearnPorts

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VLAN

 

 

 

 

 

 

 

 

 

 

 

Ports

 

 

 

 

 

Header

 

 

 

 

 

Reset to

VLANnPorts

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compare

 

 

 

IALE

 

 

All 1s

 

 

 

 

VLAN IDs

Header

 

Header

 

 

 

 

 

 

 

 

 

 

Stripped

 

 

 

 

 

 

 

 

 

 

Retained

 

 

 

 

 

 

 

 

If (equal or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

txacc = 1)

IEEE Std

 

 

 

 

 

 

 

 

 

 

Then Strip Header,

 

Non-

 

 

 

 

 

 

 

 

802.1Q

 

 

 

 

 

 

 

 

 

Otherwise,

IEEE Std

 

 

 

 

 

 

 

 

Format

 

 

 

 

 

 

 

 

Keep Header

 

802.1Q

 

 

 

 

 

 

 

 

Frame

 

 

 

 

 

 

 

 

 

 

 

 

 

Format

 

 

 

 

 

 

 

 

 

Header

 

 

 

 

 

 

 

 

 

 

 

Frame

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transmit

Figure 8. VLAN Overview

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

39

Image 39
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice