Texas Instruments TNETX3270 specifications Received Pretag Port Assignments, Tag, Port 27 NM

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

port-routing-code pretag on reception

If the pretag bit is set to 1 in the appropriate Portxcontrol register, during the seven MxxRCLK cycles prior to MxxRXDV going high, the port expects to receive a seven-nibble pretag on MxxRXD3±MxxRXD0 (see Figure 4).

MxxRCLK

MxxRXD3±

Tag 6

Tag 5

Tag 4

Tag 3

Tag 2

Tag 1

Tag 0

Preamble and Frame

MxxRXD0

 

 

 

 

 

 

 

 

MxxRXDV

Figure 4. Port-Routing-Code Pretag

Each of the 28 bits contained within these nibbles represents a destination port for the frame. If a bit is 1, the frame is queued to that port. If the port is disabled or its link is inactive, the frame subsequently is drained from the port's queue, which again returns to zero length.

The port assignments for these tag bits are shown in Table 6.

Table 6. Received Pretag Port Assignments

TAG

MxxRXD3

MxxRXD2

MxxRXD1

MxxRXD0

 

 

 

 

 

6

Port 27 (NM)

Port 26

Port 25

Port 24

 

 

 

 

 

5

Port 23

Port 22

Port 21

Port 20

 

 

 

 

 

4

Port 19

Port 18

Port 17

Port 16

 

 

 

 

 

3

Port 15

Port 14

Port 13

Port 12

 

 

 

 

 

2

Port 11

Port 10

Port 09

Port 08

 

 

 

 

 

1

Port 07

Port 06

Port 05

Port 04

 

 

 

 

 

0

Port 08

Port 02

Port 01

Port 00

 

 

 

 

 

The 28 bits are examined during the reception process to see if just one destination bit is set. If this is the case, the frame is received and handled like a unicast frame (such frames can be cut through). If more than one bit is set, the frame is handled as an in-order-broadcast (and cannot be cut through). The frame is routed to all the port(s) specified regardless of whether the destination address is unicast or multicast (i.e., the destination address is not examined).

If all 28 tag bits are 0, the frame is discarded. If the frame has not been discarded in the MAC (for some reason), the portx-filtered RX-frames statistic is incremented.

The tag bits are not examined to see if the source port is specified as a destination port, so it is possible, for example, for port 25 to send a frame to itself by setting bit 1 in tag 6.

The IALE sees and processes pretagged frames exactly as nonpretagged frames (it does not know that a frame has been pretagged). However, the final port-routing code generated by the IALE is ignored (the information in the pretag determines the destination ports). Normal IALE behavior occurs in terms of address learning and interrupt generation and statistics updates with one exception ± the portx-filtered RX-frames statistic is incremented if the pretag contained all 0s. (Whether or not the IALE generates its own (ignored) port-routing code of all 0s has no effect on this statistic if the frame is a pretagged frame.)

Since the IALE's routing decision is ignored on pretagged frames, the Txblockports, Rxuniblockports, and Rxmultiblockports registers have no effect on frame reception or transmission.

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice