Texas Instruments TNETX3270 With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports, Description

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

description

The TNETX3270 provides highly integrated switching solutions that allow network designers to lower overall system costs. Based on Texas Instruments (TI ) ThunderSWITCH architecture, the TNETX3270 design integrates 24 full-duplex 10-Mbit/s ports and 3 full-duplex 10-/100-Mbit/s ports, as well as an address-lookup engine, all in a single 240-pin package. All ports on the TNETX3270 are designed to support multiple addresses, cut-through or store-and-forward modes of operation, and VLAN. The 10-/100-Mbit/s ports have media-independent interface (MII)-compatible interfaces and can be configured to work as MII uplinks to high-speed switching fabrics. All three of the 10-/100-Mbit/s ports can be logically combined into a single high-performance uplink channel that can be used to provide up to 600-Mbit/s switch-to-switch connections.

The TNETX3270 incorporates an internal content-addressable memory (CAM) capable of supporting 2,048 end stations from a single switch. In addition, the device supports 32 user-configurable VLAN-broadcast domains (IEEE Std 802.1Q), which allows IEEE Std 802.1P priority support interoperability, IEEE Std 802.3X full-duplex flow control, and a collision-based flow-control scheme. The TNETX3270 also integrates an EEPROM interface that allows the device to be initialized and configured without the added expense of a CPU. All of these features on chip greatly reduce the number of external components required to build a switch.

The internal address-lookup engine (IALE) supports up to 2K unicast/multicast and broadcast addresses and up to 32 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown source- and destination-address packets to ports specified via programmable masks.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice