Texas Instruments TNETX3270 specifications 10-/100-Mbit/s port configuration in a managed switch

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

10-/100-Mbit/s port configuration in a managed switch

The 10-/100-Mbit/s ports can be configured in a managed switch using either of the following procedures:

1.The management CPU sets the req10 and reqhd bits of the Portxcontrol registers as required while the PHYs are held in reset. If either of these bits becomes a 1, the corresponding terminal is not pulled low and thus, floats high. (The reqnp bit also can be loaded from EEPROM to enable/disable pause-frame control in the MAC, but this cannot be communicated to the PHY. The system designer should ensure that the MAC and PHY operate using the same pause-frame regime.)

2.The PHYs are then released from reset and either:

a.Look at the MxxFORCE10 and MxxFORCEHD terminals and configure themselves as specified (if not autonegotiating), or as the highest common denominator with the link partner, if they are autonegotiating.

b.Ignore TNETX3270 requests and configure themselves in some other manner.

3.The PHYs (or external system) subsequently drive MxxFORCE10 and MxxFORCEHD low for those features that are supported only at the lower performance. These are continuously sampled into the Portxstatus register.

4.The MACs then operate as indicated by the Portxstatus register.

5.The operating state of the PHYs subsequently can be altered by using the IEEE Std 802.3u MII management interface. Any change of state should be reflected on the values presented on MxxFORCE10 and MxxFORCEHD so that the MACs are similarly reconfigured.

Or:

1.MxxFORCE10 and MxxFORCEHD should not be connected to anything.

2.Software uses the IEEE Std 802.3u MII management interface to configure the PHYs to the required operating conditions, possibly interrogating the PHY as to the results of autonegotiation.

3.The MACs should then be set to operate in the required manner by writing the appropriate values to the req10 and reqhd bits in the Portxcontrol register. This causes MxxFORCE10 and MxxFORCEHD to reflect the operating conditions that are sampled into the Portxstatus registers to configure the MACs. The reqnp bit also should be set to 1 for those PHYs that are configured to support IEEE Std 802.3x pause frames. This also is communicated to the MACs.

SDRAM interface

All valid frames pass over this interface to the external SDRAM, where they are temporarily buffered between reception and transmission.

The data bus within the SDRAM interface is 32 bits wide and supports the following configurations:

DTwo 1M ⋅ 16-bit SDRAMs (4 Mbytes of storage)

DFour 2M ⋅ 8-bit SDRAMs (8 Mbytes of storage)

DTwo 4M ⋅ 16-bit SDRAMs (16 Mbytes of storage)

DFour 8M ⋅ 8-bit SDRAMs (32 Mbytes of storage)

The interface is clocked at 83.33 MHz, so 12-ns SDRAMS are required. If one of the above configurations is used, then no additional glue logic is required. The SDRAMs should be connected to the SDRAM interface pins (see Table 15).

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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