Texas Instruments TNETX3270 specifications Port trunking/load sharing, Flow control

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

port trunking/load sharing

Port trunking is a technique that allows two or more ports to be parallel connected between switches and counted as one port to increase the bandwidth between those devices. The trunking algorithm determines on which of these ports a frame is transmitted, spreading the load evenly across these ports and maintaining packet order.

The TNETX3270 supports trunking on the 10-/100-Mbit/s ports. Trunk-port determination is the final step in the IALE frame-routing algorithm. Once the destination port(s) for a frame has been determined, the port-routing code is examined to see if any of the destination ports are members of the trunk. If so, the trunking algorithm is applied to select which port within that trunk transmits the frame ± it may or may not be the one currently in the port-routing code. To determine the destination port within a trunk, bits 3±1 of the source and destination address are XORed to produce a map index. This map index is used to index to a group of eight internal registers to determine the destination port. The actual transmit port of a unicast packet is dynamic, based on the eight internal registers.

Load sharing is similar to trunking, with the following differences:

DIf the destination address was found in the IALE records when it was looked up, the port-routing code is not adjusted by the load-sharing/-trunking algorithm.

DThe 3-bit map index is determined only from the source address as follows:

±Bits 47±32 are XORed to produce the most significant bit of the map index.

±Bits 31±16 are XORed to produce the middle of the map index.

±Bits 15±0 are XORed to produce the least significant bit of the map index.

Once assigned, the tx port for a unicast packet is static.

flow control

The switch incorporates two forms of flow control: collision based, and IEEE Std 802.3 pause frames.

In either case, the switch recognizes when it is becoming congested by monitoring the size of the free-buffer queue. When the number of free buffers drops below the specified threshold, the switch prevents frames from entering the device by issuing the flow control appropriate to each port's current mode of operation. This prevents reception of any more frames on those ports until the frame backlog is reduced and the number of free buffers has risen above the threshold, at which point flow control ceases and frames again can be received. The default free-buffer threshold after a hardware reset is chosen to ensure that all ports simultaneously can start reception of a maximum-length frame and ensure complete reception.

The purpose of flow control is to reduce the risk of data loss if a long burst of activity caused the switch to backlog frames to the point where the memory system is full. However, there is no way to prevent frame reception on those ports operating in full-duplex mode that have not negotiated IEEE Std 802.3 flow control. Such ports can exhaust the free buffer queue, with subsequent data loss.

Each 10-/100-Mbit/s port can request collision or IEEE Std 802.3X flow control through internal registers.

Flow control is globally enabled/disabled. Each individual port can request half- or full-duplex or IEEE Std 802.3 flow to be negotiated by the PHY device.

In full duplex, a port does not start transmitting a new frame if the collision pin is active, although the value of this pin is ignored at other times.

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice