Texas Instruments TNETX3270 Receive filtering of frames, Data transmission, Transmit control

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

receive filtering of frames

Received frames that contain an error (e.g., CRC, alignment, jabber, etc.) are discarded before transmission and the relevant statistics counter is updated.

data transmission

The MAC takes data from the TNETX3270 internal buffer memory and passes it to the PHY. The data also is synchronized to the transmit clock rate.

A CRC block verifies that the outgoing frame has not been corrupted within the switch by verifying that it still has a valid CRC as the frame is being transmitted. If a CRC error is detected, it is counted in the transmit data errors counter.

transmit control

The frame control block handles the output of data to the PHYs. Several error states are handled. If a collision is detected, the state machine jams the output. If the collision was late (after the first 64-byte buffer has been transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While operating in full duplex, both carrier-sense (CRS) mode and collision-sensing modes are disabled (the switch does not start transmitting a new frame if collision is active in full-duplex mode).

Internally, frame data only is removed from buffer memory once it has been successfully transmitted without collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision is detected, frame recovery and retransmission are initiated.

adaptive performance optimization (APO) (transmit pacing)

Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled, the MAC uses transmission pacing to enhance performance (when connected on networks using other transmit pacing-capable MACs). Adaptive performance pacing introduces delays into the normal transmission of frames, delaying transmission attempts between stations, reducing the probability of collisions occurring during heavy traffic (as indicated by frame deferrals and collisions), thereby, increasing the chance of successful transmission.

When a frame is deferred, suffers a single collision, multiple collisions, or excessive collisions, the pacing counter is loaded with an initial value of 31. When a frame is transmitted successfully (without a deferral, single collision, multiple collision, or excessive collision), the pacing counter is decremented by 1, down to 0.

With pacing enabled, a new frame is permitted to immediately [after one inter-packet gap (IPG)] attempt transmission only if the pacing counter is 0. If the pacing counter is not 0, the frame is delayed by the pacing delay (a delay of approximately four interframe gap delays).

NOTE:

APO affects only the IPG preceding the first attempt at transmitting a frame. It does not affect the backoff algorithm for retransmitted frames. APO should be used only with other endstations that also support APO.

interframe gap enforcement

The measurement reference for the interpacket gap of 96-bit times is changed, depending on frame traffic conditions. If a frame is transmitted successfully (without collision), 96-bit times is measured from MxxTXEN. If the frame suffered a collision, 96-bit times is measured from MxxCRS.

backoff

The device implements the IEEE Std 802.3 binary exponential backoff algorithm.

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±2610-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
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