Texas Instruments TNETX3270 Hardware configurations, LED Status Bit Definitions and Shift Order

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Table 10. LED Status Bit Definitions and Shift Order

ORDER

NAME

FUNCTION

 

 

slast = 0

slast = 1

 

 

 

 

 

 

1±7

1±7

0

Zero. Dummy data for first seven of 48 LEDCLK cycles.

 

 

 

 

 

 

 

Software LEDs 0±11. These allow additional software-controlled status to be displayed. These

8±19

35±46

SW0±SW11

12 LEDs reflect the values of bits 0±11 of the swled field in LEDControl at the moment that the LED

interface samples them. If this occurs between writes to the most significant and least significant

 

 

 

 

 

 

bytes of LEDControl, these values appear on the LEDs, separated by 1/16th of a second.

 

 

 

 

 

 

 

Port status LEDs 00±26. These 27 LEDs indicate the status of ports 00±26, in this order (port 00

 

 

 

is output first). Note that port 27 (management port) does not have an LED. The transmit multicast

20±46

8±34

P00±P26

content of these bits can be controlled by the txais bit in LEDControl. Note that IEEE Std 802.3X

pause frames never appear on the LEDs as port activity. The port's LED toggles each 1/16th of a

 

 

 

 

 

 

second if there was any frame traffic (other than pause frames) on the port during the previous

 

 

 

1/16th of a second.

 

 

 

 

47

47

FLOW

Flow control. LED is on when the internal flow control is enabled and active. Active means that flow

control is asserted during the previous 1/16th of a second.

 

 

 

 

 

 

 

 

 

 

Fault. LED indicates:

 

 

 

± the EEPROM CRC is invalid.

 

 

 

± an external DRAM parity error has occurred.

48

48

FAULT

± the fitled in LEDControl has been set.

 

 

 

The CRC and parity error indications are cleared by hardware reset (terminal or DIO). The CRC

 

 

 

error indication also is cleared by setting load to 1. The parity error indication also is cleared by

 

 

 

setting start to 1.

 

 

 

 

lamp test

When the device is in the hardware reset state, LEDDATA is driven high and LEDCLK runs continuously. This causes all LEDs to be illuminated and serves as a lamp test function.

multi-LED display

The LED interface is intended to provide the lowest-cost display with a single multifunction LED per port. In systems requiring a full-feature display (more than levels of activity) using multiple LEDs per port, this can be achieved by driving the LEDs directly from the PHY signals.

hardware configurations

10-Mbit/s MAC interfaces (ports 00±23)

Each group of eight 10-Mbit/s ports (ports 00 to 07, 08 to 15, and 16 to 23) interfaces directly with a TI TNETE2008, which contains eight 10-Mbit/s PHYs. This interface is time multiplexed between the eight ports, with receive and transmit data being transferred over nibble-wide buses. Any given port needs only to transfer data at 2.5 MHz (i.e., 2.5 MHz ⋅4 bits = 10 Mbit/s), but because TNETE2008 contains eight PHYs, the frequency of nibble transfers is 20 MHz (i.e., 2.5 MHz ⋅ 8 ports). The remaining control and status signals also are transferred at this rate.

Table 11 shows how the terminals of a TNETE2008 device are connected to each 10-Mbit/s interface on the TNETX3270.

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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