Texas Instruments TNETX3270 Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40, Findport

Page 17

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Table 2. Detailed DIO Register Map (Continued)

BYTE 3		BYTE 2		BYTE 1		BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

Findnode<23±16>		Findnode<31±24>		Findnode<39±32>		Findnode<47±40>	0x0440

FindVLAN		Findcontrol		Findnode<7±0>		Findnode<15±8>	0x0444

			Findport				0x0448

Newnode<23±16>		Newnode<31±24>		Newnode<39±32>		Newnode<47±40>	0x044C

	Reserved			Newnode<7±0>		Newnode<15±8>	0x0450

	NewVLAN			Newport			0x0454

Addnode<23±16>		Addnode<31±24>		Addnode<39±32>		Addnode<47±40>	0x0458

AddVLAN		Adddelcontrol		Addnode<7±0>		Addnode<15±8>	0x045C

			Addport				0x0460

Agednode<23±16>		Agednode<31±24>		Agednode<39±32>		Agednode<47±40>	0x0464

AgedVLAN		Agedport		Agednode<7±0>		Agednode<15±8>	0x0468

Delnode<23±16>		Delnode<31±24>		Delnode<39±32>		Delnode<47±40>	0x046C

DelVLAN		Delport		Delnode<7±0>		Delnode<15±8>	0x0470

Agingcounter				Numnodes			0x0474

			Reserved				0x0478:0x07FF

	Reserved			DMAaddress			0x0800

Reserved				Int			0x0804

Reserved				Intenable			0x0808

Systest				Freestacklength			0x080C

		RAMaddress					0x0810

		Reserved				RAMdata	0x0814

	Reserved			NMRxcontrol			0x0818

Reserved				NMTxcontrol			0x081C

		Reserved				NMdata	0x0820

			Reserved				0x0824:0x3FFF

		TNETX3270 reset: reinitializes the TNETX3270					0x4000:0x5FFF

			Reserved				0x6000:0x7FFF

		Port and network management port statistics					0x8000:8DFF

			Reserved				0x8E00:8FFF

		TX pause, RX pause, and security-violation counters					0x9000:0x91BF

			Reserved				0x91C0:0x9FFF

		Unknown unicast destination addresses					0xA000

		Unknown multicast destination addresses					0xA004

		Unknown source address					0XA008

			Reserved				0xA00C:0xFFFF

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

17

Image 17

Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice