Texas Instruments TNETX3270 Speed Configuration ± MxxFORCE10, Duplex Configuration ± MxxFORCEHD

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

10-/100-Mbit/s port configuration (continued)

Each terminal is considered to be bidirectional, when pulled low by either TNETX3270 or by the PHY (or other external connections). If neither pulls the terminal low, then the pullup resistor maintains a value of 1 on the terminal. When the PHY does not pull down a terminal, then it can determine the desired option that is being requested by TNETX3270. TNETX3270 observes the terminal to determine if its desired option has been granted.

The sense of these three signals is such that the higher-performance option is represented by a value of 1; if the MAC does not require the higher performance or the PHY cannot supply it, either can pull the signal low, forcing the port to use the lower-performance option.

The status of the link for each of these ports is indicated on the MxxLINK terminal and observable in the port's Portxstatus register. The MxxLINK terminal plays no part in the negotiation of speed or duplex or their recording in the Portxstatus register.

The behavior of these terminals is summarized in Tables 13 and 14.

Table 13. Speed Configuration ± MxxFORCE10

Portxcontrol

 

 

 

 

 

Portxstatus

OUTCOME

 

MxxFORCE10

 

req10

 

 

SPEED

(Mbit/s)

 

 

 

 

 

 

 

 

 

 

 

 

0

 

Floating 1

1

100

 

 

 

 

 

 

1

Driven 0 (by TNETX3270)

0

10

 

 

 

 

 

 

X

 

Driven 0 (by PHY)

0

10

 

 

 

 

 

 

 

 

Table 14. Duplex Configuration ± MxxFORCEHD

Portxcontrol

 

 

 

 

 

Portxstatus

OUTCOME

 

MxxFORCEHD

 

reqhd

 

 

DUPLEX

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

Floating 1

1

Full duplex

 

 

 

 

 

 

1

Driven 0 (by TNETX3270)

0

Half duplex

 

 

 

 

 

 

X

 

Driven 0 (by PHY)

0

Half duplex

 

 

 

 

 

 

 

 

10-/100-Mbit/s port configuration in a nonmanaged switch

The 10-/100-Mbit/s ports can be configured in a nonmanaged switch using the following procedure:

1.The EEPROM loads the req10 and reqhd bits of the Portxcontrol registers as required. If either of these bits becomes a 1, the corresponding terminal is not pulled low and thus, floats high. (The reqnp bit also can be loaded from EEPROM to enable/disable pause-frame control in the MAC, but this cannot be communicated to the PHY. The system designer should ensure that the MAC and PHY operate using the same pause-frame regime.)

2.The PHYs either:

a.Look at the MxxFORCE10 and MxxFORCEHD terminals and configure themselves as specified (if not autonegotiating), or as the highest common denominator with the link partner, if they are autonegotiating. If the PHYs use the information on these terminals, they must wait until TNETX3270 loads the EEPROM contents before doing so (this may require delaying the reset to the PHYs if necessary).

b.Ignore TNETX3270 requests and configure themselves in some other manner.

3.The PHYs (or external system) then drive MxxFORCE10 and MxxFORCEHD low for those features that are supported only at the lower performance. These are continuously sampled into the Portxstatus register.

4.The MACs then operate as indicated by the Portxstatus register.

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±2610-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice