Texas Instruments TNETX3270 specifications Terminal Internal Description Name RESISTOR³

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Terminal Functions

10-Mbit/s MAC multiplexed interface (ports 00±23) is multiplexed into three groups (TH0, TH1, and TH2) of eight ports²

 

TERMINAL

 

I/O

INTERNAL

 

DESCRIPTION

 

NAME

NO.

RESISTOR³

 

 

 

 

 

 

 

 

TH0CLK

222

 

 

Interface clock. Eight ports are supported on each interface and use this common 20-MHz

 

TH1CLK

2

I

Pullup

 

clock.

 

 

 

 

TH2CLK

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0COL

223

 

 

Interface collision sense. Assertion of THxCOL² during half-duplex operation indicates

 

TH1COL

3

I

Pulldown

network collision on the current port. Additionally, during full-duplex operation, transmission

 

TH2COL

24

 

 

of new frames does not start if this terminal is asserted.

 

 

 

 

 

 

 

 

 

 

 

TH0CRS

224

 

 

Interface carrier sense. THxCRS²

indicates a frame carrier signal is being received on a

 

TH1CRS

5

I

Pulldown

 

current port.

 

 

 

 

TH2CRS

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0LINK

232

 

 

Interface link presence. THxLINK²

indicates the presence of the connection on a port.

 

TH1LINK

13

I

Pulldown

± Low = no link

 

 

 

 

TH2LINK

32

 

 

± High = link good

 

 

 

 

 

 

 

 

 

 

 

 

 

 

213

 

 

Interface renegotiate. A 1-0-1 sequence output on

 

causes flow control and

 

TH0RENEG

 

 

 

THxRENEG

 

TH1RENEG

233

O

None

half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.

 

TH2RENEG

15

 

 

These THxRENEG terminals connect to IFFORCEHD on TNETE2008.

 

 

 

 

 

 

 

 

 

 

TH0RXD3

231

 

 

 

 

 

 

 

TH0RXD2

230

 

 

 

 

 

 

 

TH0RXD1

228

 

 

 

 

 

 

 

TH0RXD0

227

 

 

 

 

 

 

 

TH1RXD3

11

 

 

Interface receive data. The receive data nibble from the current port is synchronous to

 

TH1RXD2

10

I

Pullup

THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.

 

TH1RXD1

9

THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals

 

 

 

 

TH1RXD0

7

 

 

also are used to report the channel state to the MAC.

 

TH2RXD3

30

 

 

 

 

 

 

 

TH2RXD2

29

 

 

 

 

 

 

 

TH2RXD1

28

 

 

 

 

 

 

 

TH2RXD0

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0TXEN

219

 

 

 

 

 

 

 

TH1TXEN

240

O

None

Interface transmit enable. THxTXEN indicates valid transmit data on THxTXD.

 

TH2TXEN

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH0SYNC

221

 

 

Interface synchronize. THxSYNC

is used to synchronize the port traffic between the

 

 

 

media-access controller (MAC) and PHY. When THxSYNC is a 1, the current MAC-to-PHY

 

TH1SYNC

1

I

Pullup

 

path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface

 

TH2SYNC

22

 

 

 

 

 

TH2. THxSYNC is sampled by the MAC on the falling edge of THxCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

² THx = TH0, TH1, and TH2

³Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required in their system.

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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