Texas Instruments TNETX3270 specifications SPWS043B ± November 1997 ± Revised April

Page 43

 

 

 

 

 

 

 

TNETX3270

 

 

 

 

 

ThunderSWITCH

24/3 ETHERNET

SWITCH

 

 

 

 

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

 

 

 

 

 

 

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

 

 

 

 

A

 

 

 

B

 

 

 

 

Source

 

Source

new

 

 

 

 

 

No

No

 

 

 

 

 

Port = 1 in

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

NLearnPorts?

 

 

 

 

 

 

Found?

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Yes

 

 

 

 

 

 

 

Yes

Source

 

 

 

 

 

 

 

Locked

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit = 1?

 

 

 

 

 

 

 

 

No

 

 

 

 

 

 

 

 

Source

No

 

AND UnkSrcPorts

 

 

 

 

 

Port

 

 

 

 

 

 

 

 

With VLAN

 

 

 

 

 

Moved?

 

 

 

 

 

 

 

 

 

VLANnports,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Yes

Then OR With

 

 

 

 

 

Yes

 

 

Port Routing Code

 

 

 

 

 

 

 

 

 

secvio

 

 

 

 

 

 

Unknown

 

Source

 

 

Stayed

 

 

Source

 

Yes

 

No

 

 

 

 

 

 

 

 

Secure

 

Within a

 

 

 

 

 

 

 

 

 

 

 

 

Bit = 1?

 

 

Trunk?

 

 

 

 

Source

 

 

 

 

 

 

 

 

Port

No

 

 

 

 

 

 

 

Security

chng

 

Yes

 

 

 

 

Violation

 

 

 

 

 

 

 

 

 

 

 

 

 

Discard

 

 

 

Yes

 

 

 

 

Frame

 

 

 

 

 

 

 

 

 

 

 

 

Source

Yes

 

 

 

 

 

 

 

Port = 1 in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RingPorts?

 

 

 

 

 

 

 

 

No

 

 

 

 

 

 

 

 

Remove Source Port

 

 

 

 

 

 

 

(and other trunk members)

 

 

 

 

 

 

 

From

 

 

 

 

 

 

 

 

Port Routing Code

 

 

 

 

To C

(Continued)

Figure 9. Frame-Routing Algorithm (Continued)

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

43

Page 42 Page 44
Image 43
Page 42 Page 44
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
Top Page Image Contents