Texas Instruments TNETX3270 specifications Receive versus transmit priority, Uplink pretagging

Page 24

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

receive versus transmit priority

The queue manager prioritizes receive and transmit traffic as follows:

DHighest priority is given to frames that currently are being transmitted. This ensures that transmitting frames do not underrun.

DNext priority is given to frames that are received if the free-buffer stack is not empty. This ensures that received frames are not dropped unless it is impossible to receive them.

DLowest priority is given to frames that are queued for transmission but have not yet started to transmit. These frames are promoted to the highest priority only when there is spare capacity on the memory bus.

DThe NM port receives the lowest priority to prevent frame loss during busy periods.

The memory bus has enough bandwidth to support the two highest priorities. The untransmitted frame queues grow when frames received on different ports require transmission on the same port(s) and when frames are repeatedly received on ports that are at a higher speed than the ports on which they are transmitted. This is likely to be exacerbated by the reception of multicast frames, which typically require transmission on several ports. When the backlog grows to such an extent that the free buffer stack is nearly empty, flow control is initiated (if it has been enabled) to limit further frame reception.

uplink pretagging

TNETX3270 can be incorporated into a switch where routing decisions can be made at a higher level. To facilitate this, two forms of tags are provided on ports 24±26:

DSource-port pretag on transmission

DPort-routing-code pretag on reception

source-port pretag on transmission

Ports 24±26 provide the frame's source-port-number pretag one cycle before MxxTXEN goes high (this tag is ignored by an externally connected PHY). The 5-bit tag appears as an encoding on terminals MxxTXER and MxxTXD3 to MxxTXD0 (most significant bit to least significant bit). This is shown in Figure 3 and Table 5.

MxxTCLK
MxxTXER	Tag MSB	Transmit Error
MxxTXD3±MxxTXD0	Tag LS 4 Bits	Preamble and Frame

MxxTXEN

Figure 3. Source-Port Pretag

24	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 24

Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice