Texas Instruments TNETX3270 Terminal Functions, 10-/100-Mbit/s MAC interface ports 24±26 ²

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

				Terminal Functions (Continued)
	10-/100-Mbit/s MAC interface (ports 24±26) (continued)²
	TERMINAL		I/O	INTERNAL	DESCRIPTION
	NAME	NO.	I/O	RESISTOR	DESCRIPTION
	NAME	NO.		RESISTOR

	M24RXD3	49
	M24RXD2	48
	M24RXD1	47
	M24RXD0	46
	M25RXD3	73			Receive data (nibble receive data from the attached PHY or PMI device). Data on these
	M25RXD2	71
	M25RXD2	71	I	Pullup	signals is synchronous to MxxRCLK. MxxRXD0 is the least significant bit and MxxRXD3
	M25RXD1	70	I	Pullup
	M25RXD1	70			is the most significant bit.
	M25RXD0	69			is the most significant bit.
	M25RXD0	69
	M26RXD3	98
	M26RXD2	97
	M26RXD1	96
	M26RXD0	95

	M24RXDV	50			Receive data valid. When high, MxxRXDV indicates valid data is present on the
	M25RXDV	75	I	Pulldown
	M25RXDV	75	I	Pulldown	MxxRXD3±MxxRXD0 lines.
	M26RXDV	99			MxxRXD3±MxxRXD0 lines.
	M26RXDV	99

	M24RXER	51
	M25RXER	76	I	Pulldown	Receive error. MxxRXER indicates a coding error on received data.
	M26RXER	101

	M24TCLK	33
	M25TCLK	56	I	Pullup	Transmit clock. Transmit clock source from the attached PHY or PMI device.
	M26TCLK	82

	M24TXD3	38
	M24TXD2	37
	M24TXD1	36
	M24TXD0	35
	M25TXD3	61			Transmit data (nibble transmit data). When MxxTXEN is asserted, these signals carry
	M25TXD2	60
	M25TXD2	60	O	None	transmit data. Data on these signals is synchronous to MxxTCLK. MxxTXD0 is the least
	M25TXD1	59	O	None
	M25TXD1	59			significant bit and MxxTXD3 is the most significant bit.
	M25TXD0	57			significant bit and MxxTXD3 is the most significant bit.
	M25TXD0	57
	M26TXD3	86
	M26TXD2	85
	M26TXD1	84
	M26TXD0	83

	M24TXEN	39
	M25TXEN	62	O	None	Transmit enable. MxxTXEN indicates valid transmit data on MxxTXD3±MxxTXD0.
	M26TXEN	87

	M24TXER	41			Transmit error. MxxTXER allows coding errors to be propagated across the MII. MxxTXER
	M24TXER	41			is taken high when an under-run in the transmit FIFO for port xx occurs and causes fill data
	M25TXER	63	O	None
	M25TXER	63	O	None	to be transmitted (MxxTXER is low otherwise). MxxTXER is asserted at the end of an
	M26TXER	89
	M26TXER	89			under-running frame, enabling the device to force a coding error.

²xx = ports 24, 25, and 26

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 8

Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice