Texas Instruments TNETX3270 specifications DIO/DMA read cycle

Page 59

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

DIO/DMA read cycle

timing requirements (see Figure 19)

NO.

MIN MAX

UNIT

1

tw(SCSL)

Pulse duration,

low

ns

SCS

2

tw(SCSH)

Pulse duration,

high

14

ns

SCS

3

tsu(SRNW)

Setup time,

high before

↓

0

ns

SRNW

SCS

4

tsu(SAD)

Setup time, SAD1±SAD0 and

valid before

↓

0

ns

SDMA

SCS

operating characteristics over recommended operating conditions (see Figure 19)

NO.

PARAMETER

MIN

MAX

UNIT

5

tw(SRDYH)

Pulse duration,

high

12

ns

SRDY

6

td(SRNW)

Delay time, from

↓ to

↓

0

ns

SRDY

SRNW

7

td(SAD)

Delay time, from

↓ to SAD1±SAD0 and

invalid

0

ns

SRDY

SDMA

8

td(SCS)

Delay time, from

↓ to

↑

0

ns

SRDY

SCS

9

td(SRDY)

Delay time, from SDATA7±SDATA0 to

↓

0

ns

SRDY

10

td(SRDYZH)

Delay time, from

↓ to

↑

0

ns

SCS

SRDY

11

t

Delay time, from

↓ to

↓²

0

ns

SCS

SRDY

d(SRDY)2

12

td(SDATAZ)

Delay time, from

↑ to SDATA7±SDATA0 Z state

0

6

ns

SCS

13

td(SRDY)3

Delay time, from

↑ to

↑

0

12

ns

SCS

SRDY

²When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25±100 ms) between SCS being asserted and SRDY being asserted.

	1		2
4	11		13
3	10	8	12
SCS
(input)
		6
SRNW
(input)
		7

SAD1±SAD0,

SDMA (inputs)

		9
SDATA7±	Z	Z
SDATA0
(outputs)		5
		5
SRDY	Z
SRDY
(output)

Figure 19. DIO/DMA Read Cycle

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

59

Image 59

Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±2610-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice