Texas Instruments TNETX3270 specifications 10-/100-Mbit/s MAC interface ports 24±26³

Page 7

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Terminal Functions (Continued)

10-Mbit/s MAC multiplexed interface (ports 00±23) is multiplexed into three groups (TH0, TH1, and TH2) of eight ports² (continued)

TERMINAL

 

I/O

INTERNAL

DESCRIPTION

NAME

NO.

RESISTOR

 

 

 

 

 

 

 

TH0TXD3

218

 

 

 

TH0TXD2

217

 

 

 

TH0TXD1

216

 

 

 

TH0TXD0

215

 

 

 

TH1TXD3

239

 

 

Interface transmit data. The transmit data nibble for the current port is synchronous to

TH1TXD2

237

O

None

THxCLK. When THxTXEN is asserted, these signals carry data. THxTXD3±THxTXD0 are

TH1TXD1

236

used during renegotiation to convey flow-control and duplex configuration requests to the

 

 

TH1TXD0

234

 

 

PHY. THxTXD0 is the least significant bit and THxTXD3 is the most significant bit.

TH2TXD3

20

 

 

 

TH2TXD2

19

 

 

 

TH2TXD1

18

 

 

 

TH2TXD0

16

 

 

 

 

 

 

 

 

TH0RXDV

226

 

 

Interface receive data valid. When THxRXDV is a 1, it indicates that the THxRXD lines contain

TH1RXDV

6

I

Pulldown

valid data.

TH2RXDV

26

 

 

 

 

 

 

 

 

 

 

² THx = TH0, TH1, and TH2

10-/100-Mbit/s MAC interface (ports 24±26)³

 

TERMINAL

 

I/O

INTERNAL

DESCRIPTION

 

 

NAME

NO.

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M24COL

42

 

 

Collision sense. Assertion of MxxCOL in half-duplex signal indicates a network collision

 

M25COL

65

I

Pulldown

on that port. In full-duplex operation, transmission of new frames does not start if this

 

M26COL

90

 

 

terminal is asserted.

 

 

 

 

 

 

 

 

 

 

 

M24CRS

43

 

 

 

 

 

M25CRS

66

I

Pulldown

Carrier sense. MxxCRS indicates a frame carrier signal is being received.

 

M26CRS

92

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speed selection (force 10 Mbit/s is active low)

 

 

 

 

54

 

 

 

 

M24FORCE10

 

 

I/O§

 

± If pulled low by either the TNETX3270 or a PHY, the port operates at 10 Mbit/s.

 

M25FORCE10

80

Pullup

± If not pulled low by either the TNETX3270 or a PHY, the internal pullup resistor holds

 

M26FORCE10

104

 

 

Ω

pullup resistor

 

 

 

 

this signal high and the port operates at 100 Mbit/s. An external 4.7-k

 

 

 

 

 

 

 

connected to VDD(3.3V) may be required, depending on the system layout.

 

M24LINK

52

 

 

Connection status. MxxLINK indicates the presence of a port connection.

 

 

M25LINK

78

I

Pulldown

± If MxxLINK = 0, there is no link.

 

 

M26LINK

102

 

 

± If MxxLINK = 1, the link is good.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Duplex selection (force half duplex is active low)

 

 

 

53

 

 

 

 

M24FORCEHD

 

I/O³

 

± If pulled low by either the TNETX3270 or the PHY, the port operates at half duplex.

 

M25FORCEHD

79

Pullup

± If not pulled low by either the TNETX3270 or the PHY, the internal pullup resistor holds

 

M26FORCEHD

103

 

 

Ω

pullup resistor

 

 

 

 

this signal high and the port operates at full duplex. An external 4.7-k

 

 

 

 

 

 

 

connected to VDD(3.3V) may be required, depending on the system layout.

 

M24RCLK

44

 

 

 

 

 

M25RCLK

67

I

Pullup

Receive clock. Receive clock source from the attached PHY or PMI device.

 

M26RCLK

93

 

 

 

 

 

 

 

 

 

 

 

 

 

³xx = ports 24, 25, and 26

§ Not a true bidirectional terminal. It can only be actively pulled down (open drain).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

Page 6 Page 8
Image 7
Page 6 Page 8
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
Top Page Image Contents