Texas Instruments TNETX3270 specifications Detailed DIO Register Map, Byte DIO Address, Sio

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TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Table 2. Detailed DIO Register Map

BYTE 3		BYTE 2		BYTE 1		BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

	Port1control				Port0control		0x0000

	Port3control				Port2control		0x0004

	Port5control				Port4control		0x0008

	Port7control				Port6control		0x000C

	Port9control				Port8control		0x0010

	Port11control				Port10control		0x0014

	Port13control				Port12control		0x0018

	Port15control				Port14control		0x001C

	Port17control				Port16control		0x0020

	Port19control				Port18control		0x0024

	Port21control				Port20control		0x0028

	Port23control				Port22control		0x002C

	Port25control				Port24control		0x0030

	Reserved				Port26control		0x0034

	Reserved				Reserved		0x0038:0x003F

Reserved		UnkVLANport		Mirrorport		Uplinkport	0x0040

	Reserved				Aging threshold		0x0044

		Reserved					0x0048:0x004F

		Nlearnports					0x0050

		Txblockports					0x0054

		Rxuniblockports					0x0058

		Rxmultiblockports					0x005C

		Unkuniports					0x0060

		Unkmultiports					0x0064

		Unksrcports					0x0068

		UnkVLANintports					0x006C

		Reserved					0x0070:0x007F

Trunkmap3		Trunkmap2		Trunkmap1		Trunkmap0	0x0080

Trunkmap7		Trunkmap6		Trunkmap5		Trunkmap4	0x0084

		Reserved				Trunkports	0x0088

		Reserved					0x008C:0x009F

Devcode		Reserved		SIO		Revision	0x00A0

		Reserved					0x00A4:0x00DF

RAMsize		Reserved			IOBcontrol		0x00E0

		Reserved					0x00E4

	Pausetime100				Pausetime10		0x00E8

		Reserved					0x00EC

Reserved			Flowthreshold				0x00F0

	Reserved				LEDcontrol		0x00F4

	Syscontrol				Statcontrol		0x00F8

14	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice