Texas Instruments TNETX3270 specifications Vlan ID, Fcs, Tpid TCI, Crc

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TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

frame format on the NM port (continued)

 

 

 

 

 

 

 

TPID (Tag Protocol Identifier)

 

 

 

 

TCI (Tag Control Information)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

0

 

0

0

0

0

0

1

0

0

0

0

0

0

0

0

 

Priority

 

cfi

 

 

 

 

 

VLAN ID

 

 

 

 

 

 

 

 

 

 

 

 

5 4 3

2 1

0 7 6

 

5 4 3

2 1

0

 

7

6

5

4

3

2 1

0 7 6

5 4

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

6

 

 

 

 

3 2 1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Destination

 

 

 

 

 

Source

 

 

802.1Q header

 

 

Length/Type

 

 

 

 

 

Data

 

 

 

 

FCS

 

 

Address

 

 

 

 

 

Address

 

 

TPID

 

 

 

TCI

 

 

 

 

 

 

 

 

 

 

(CRC-32)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 Bytes

 

 

 

 

 

6 Bytes

 

 

 

 

2 Bytes

 

2 Bytes

 

 

46±1517 Bytes

 

 

4 Bytes

 

 

 

 

 

 

2 Bytes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Odd Parity Bits

 

 

 

 

 

 

 

 

 

 

 

CRC

 

Reserved

 

 

 

 

 

 

Source

 

 

 

 

 

 

2nd

 

 

1st

 

1st

 

 

 

Reserved

 

 

 

Type

 

 

 

 

 

 

 

 

 

Port

 

 

 

 

 

 

TCI

 

 

TCI

 

TPID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

 

 

Byte

 

Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

6

 

5

 

 

 

4

 

 

3

 

2

 

 

1

 

 

0

 

7

 

 

6

5

4

 

3

2

1

0

 

Figure 2. NM Frame Format

Any device reading frames out of the NM port must expect frames to be in the format shown in Figure 2.

Frames received into the switch on the NM port also must conform to this format, with the following caveats:

Dcrc = 0 in NMRxcontrol

When the host provides a frame containing valid CRC it also must provide in the TPID field valid header parity protection and indicate via the crctype bit which type of CRC the frame contains [i.e., including the header (crctype = 0), or excluding the header (crctype = 1)]. If crctype indicates that the header is included, as for NM port transmissions, this pretends that IEEE Std 802.1Q TPID of 81±00 (ethertype constant) is present in the TPID field. If a CRC error or parity error is detected, the frame is discarded.

When crctype indicates that the header is included, the NM port regenerates CRC to exclude the header during the reception process (this converts the frame into the required internal frame format).

Dcrc = 1 in NMRxcontrol

If the switch is asked to generate a CRC word for the frame, the values in the TPID field are ignored by the NM port. The switch inserts header parity protection. It replaces the final four bytes of the frame with the calculated CRC (the values in the final four bytes provided are don't care).

In either case, the NM port inserts its own port number into the source port field in the least significant bits of the first TPID byte, sets the crctype bit to 0, and also sets the reserved bits to 0.

Frames received from the host via the NM port must contain a valid IEEE Std 802.1Q VLAN ID in the third and fourth bytes, following the source address (the NM port does not have a PortxQtag register for inserting a VLAN tag if none is provided and does not have an rxacc bit). Frames that do not contain a VLAN tag are incorrectly routed. They also can be corrupted at the transmission port(s). The header-stripping process does not verify that the two bytes after the source address are a valid IEEE Std 802.1Q TPID because there is a valid header under all other circumstances.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 State of DIO signals during hardware reset Interface description Receiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice