Epson S1C63000 manuals
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153 pages 894.2 Kb
© SEIKO EPSON CORPORATION 2001 All rights reserved 2 SEIKO EPSON CORPORATION3 The information of the product number changeConfiguration of product number Comparison table between new and previous numberS1C63 Family processors S1C63 Family peripheral products Comparison table between new and previous number of development toolsDevelopment tools for the S1C63 Family Development tools for the S1C63/88 Family 5 S1C63000 CORE CPU MANUALPREFACE CONTENTS 6 CHAPTER 4 INSTRUCTION SET7 CHAPTER 1 OUTLINE1.1 Features 1.2 Instruction Set Features 8 1.3 Block Diagram1.4 Input-OutputSignals9 Table 1.4.1(b) Input/output signal list (2)Data bus I00–I12 Instruction bus Inputs an instruction code M00–M15 16-bitdata bus D0–D3 4-bitdata bus A bidirectional data bus to connect to the RAM and I/O Bus control Data read signal Goes to a low level when the CPU reads data (from RAM, I/O) Data write Goes to a low level when the CPU writes data (to RAM, I/O) Read interrupt vector Goes to a low level when the CPU reads an interrupt vector System control Reset input A low level input resets the CPU Micro sleep USLP Goes to a low level when the CPU executes the SLP instruction The peripheral circuit stops oscillation on the basis of this signal Interrupt signal Non-maskableinterrupt request NMI It is accepted at the falling edge of an input signal to this terminal Interrupt request It is accepted by a low level signal input to this terminal Interrupt acknowledge interrupt response cycle Non-maskableinterrupt acknowledge NACK Status signal Fetch cycle Goes to a low level when the CPU fetches an instruction Stop signal STOP is low) Interrupt flag BS16 16-bitaccess Goes to a low level when the CPU accesses to a 16-bitRAM Data bus status Outputs data bus status (for both the 4-bitand 16-bitdata bus) High impedance Interrupt vector read Memory write Memory read See Chapter 3, "CPU OPERATION", for the timing of the signals 10 CHAPTER 2 ARCHITECTURECHAPTER 3 CPU OPERATION 28 3 CPU O3.1 Timing Generator and Bus Cycle 3.2 Instruction Fetch and Execution 29 3.3 Data Bus (Data Memory) Control31 3.4 Initial Reset3.4.1 Initial reset sequence 3.4.2 Initial setting of internal registers 32 3.5 Interrupts37 3.6 Standby Status3.6.1 HALT status 3.6.2 SLEEP status 39 CHAPTER 4 INSTRUCTION SET4.1 Addressing Mode 43 4.2 Instruction List65 4.3 Instruction Formats66 4.4 Detailed Explanation of Instructions67 ADC %r,%rADC %r,imm4 68 ADC %r,[%ir]ADC %r,[%ir]+ 69 ADC [%ir],%rADC [%ir]+,%r 70 ADC [%ir],imm4ADC [%ir]+,imm4 71 ADC %B,%A,n4ADC %B,[%ir],n4 72 ADC %B,[%ir]+,n4ADC [%ir],%B,n4 73 ADC [%ir],0,n474 ADC [%ir]+,0,n4ADD %r,%r 75 ADD %r,imm4ADD %r,[%ir] 76 ADD %r,[%ir]+ADD [%ir],%r 77 ADD [%ir]+,%rADD [%ir],imm4 78 ADD [%ir]+,imm4ADD %ir,%BA 79 ADD %ir,sign8AND %r,%r 80 AND %r,imm4AND %F,imm4 81 AND %r,[%ir]AND %r,[%ir]+ 82 AND [%ir],%rAND [%ir]+,%r 83 AND [%ir],imm484 BIT %r,imm485 %r,[%ir]+86 [%ir],%r[%ir]+,%r 87 BIT [%ir],imm4BIT [%ir]+,imm4 88 CALR [addr6]CALR sign8 89 CALZ imm8CLR [addr6],imm2 90 CMP %r,%r’CMP %r,imm4 91 CMP %r,[%ir]CMP %r,[%ir]+ 92 CMP [%ir],%rCMP [%ir]+,%r 93 CMP [%ir],imm4CMP [%ir]+,imm4 94 CMP %ir,imm8DEC [addr6] 95 DEC [ir],n4DEC [ir]+,n4 96 DEC %spEX %A,%B 97 EX %r,[%ir]EX %r,[%ir]+ 98 HALTINC [addr6] 99 INC [ir],n4INC [ir]+,n4 100 INC %spINT imm6 101 JP %YJR %A 102 JR %BAJR [addr6] 103 JR sign8JRC sign8 104 JRNC sign8JRNZ sign8 105 JRZ sign8LD %r,%r’ 106 LD %r,imm4LD %r,[%ir] 107 LD %r,[%ir]+LD [%ir],%r 108 LD [%ir]+,%rLD [%ir],imm4 109 LD [%ir]+,imm4LD [%ir],[%ir’] 110 LD [%ir],[%ir’]+LD [%ir]+,[%ir’] 111 LD [%ir]+,[%ir’]+LDB %BA,imm8 112 LDB %BA,[%ir]+LDB %BA,%EXT 113 LDB %BA,%rrLDB %BA,%sp 114 LDB [%ir]+,%BALDB [%X]+,imm8 115 LDB %EXT,imm8LDB %EXT,%BA 116 LDB %rr,imm8LDB %rr,%BA 117 LDB %sp,%BANOP 118 OR %r,%r’OR %r,imm4 119 OR %F,imm4OR %r,[%ir] 120 OR %r,[%ir]+OR [%ir],%r 121 OR [%ir]+,%rOR [%ir],imm4 122 OR [%ir]+,imm4POP %r 123 POP %irPUSH %r 124 PUSH %irRET 125 RETD imm8RETI 126 RETSRL %r 127 RL [%ir]RL [%ir]+ 128 RR %rRR [%ir] 129 RR [%ir]+SBC %r,%r 130 SBC %r,imm4SBC %r,[%ir] 131 SBC %r,[%ir]+SBC [%ir],%r 132 SBC [%ir]+,%rSBC [%ir],imm4 133 SBC [%ir]+,imm4SBC %B,%A,n4 134 SBC %B,[%ir],n4SBC %B,[%ir]+,n4 135 SBC [%ir],%B,n4SBC [%ir]+,%B,n4 136 SBC [%ir],0,n4SBC [%ir]+,0,n4 137 SET [addr6],imm2SLL %r 138 SLL [%ir]SLL [%ir]+ 139 SRL %r140 SRL [%ir]SRL [%ir]+ 141 SUB %r,%r’SUB %r,imm4 142 SUB %r,[%ir]SUB %r,[%ir]+ 143 SUB [%ir],%rSUB [%ir]+,%r 144 SUB [%ir],imm4SUB [%ir]+,imm4 145 TST [addr6],imm2XOR %r,%r’ 146 XOR %r,imm4XOR %F,imm4 147 XOR %r,[%ir]XOR %r,[%ir]+ 148 XOR [%ir],%rXOR [%ir]+,%r 149 XOR [%ir],imm4XOR [%ir]+,imm4 150 Index151 AMERICAEUROPE ASIAIn pursuit of “Saving” Technology, Epson electronic devices 152 “Saving” TechnologyOur lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams Epson IS energy savings 153 Core CPU Manual
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