Epson S1C63000 LD [%ir]+,%r, LD [%ir],imm4, 1 cycle, 1 cycle, Load immediate data imm4 into location [ir reg.], Load r reg. into location [ir reg.] and increment ir reg

CHAPTER 4: INSTRUCTION SET

LD [%ir]+,%r				Load r reg. into location [ir reg.] and increment ir reg.																	1 cycle
Function: [ir] ←		r, ir ← ir + 1
	Loads the content of the r register (A or B) into the data memory addressed by the ir register (X
	or Y). Then increments the ir register (X or Y).
Code:	Mnemonic			MSB														LSB
	LD [%X]+,%A				1		1	1	1	0	1	1	1	0	1	0	0		1	1EE9H
	LD [%X]+,%B				1		1	1	1	0	1	1	1	0	1	1	0		1	1EEDH
	LD [%Y]+,%A				1		1	1	1	0	1	1	1	0	1	0	1		1	1EEBH
	LD [%Y]+,%B				1		1	1	1	0	1	1	1	0	1	1	1		1	1EEFH
Flags:	E		I	C		Z
	↓		–	–		–
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Invalid

LD [%ir],imm4

Load immediate data imm4 into location [ir reg.]

1 cycle

Function: [ir] ←

imm4

Loads the 4-bit immediate data imm4 into the data memory addressed by the ir register (X or

Y).

Code:

Mnemonic

MSB

LSB

LD [%X],imm4

1

1

1

1

0

1

0

0

0

i3

i2

i1

i0

1E80H–1E8FH

LD [%Y],imm4

1

1

1

1

0

1

0

1

0

i3

i2

i1

i0

1EA0H–1EAFH

Flags:

E

I

C

Z

↓

–

–

–

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Valid

Extended

LDB

%EXT,imm8

operation: LD

[%X],imm4

[00imm8] ←

imm4 (00imm8 = 0000H + 00H to FFH)

LDB

%EXT,imm8

LD

[%Y],imm4

[FFimm8] ←

imm4 (FFimm8 = FF00H + 00H to FFH)

102 EPSON S1C63000 CORE CPU MANUAL