CHAPTER 4: INSTRUCTION SET

 

 

 

DEC [ir],n4

Decrement location [ir] in specified radix

2 cycles

Function: [ir] ← N’s adjust ([ir] - 1)

Decrements (-1) the content of the data memory addressed by the ir register (X or Y). The operation result is adjusted with n4 as the radix.

Code:

Mnemonic

 

MSB

 

 

 

 

 

 

 

 

 

LSB

 

 

 

DEC [%X],n4

 

 

1

 

1

1

0

0

1

0

0

0

n3

n2

n1

n0

1C80H–1C8FH

 

 

DEC [%Y],n4

 

 

1

 

1

1

0

0

1

0

1

0

n3

n2

n1

n0

1CA0H–1CAFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

E

I

 

C

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

↓

–

 

↕

 

 

 

↕

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode:

Src: Immediate data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dst: Register indirect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended addressing: Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended

LDB

%EXT,imm8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation: DEC

[%X],n4

 

 

[00imm8] ←

N’s adjust ([00imm8] - 1) (00imm8 = 0000H + 00H to FFH)

 

LDB

%EXT,imm8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC

[%Y],n4

 

 

[FFimm8] ←

N’s adjust ([FFimm8] - 1) (FFimm8 = FF00H + 00H to FFH)

Note: n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B.

DEC

[ir]+,n4

Decrement location [ir] in specified radix and increment ir reg.

2 cycles

Function: [ir] ←

N’s adjust ([ir] - 1), ir ←

 

ir + 1

 

 

 

 

 

 

 

 

 

 

 

 

 

Decrements (-1) the content of the data memory addressed by the ir register (X or Y). The

 

operation result is adjusted with n4 as the radix. Then increments the ir register (X or Y). The

 

increment result of the ir register does not affect the flags.

 

 

 

Code:

 

Mnemonic

MSB

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

 

 

 

DEC [%X]+,n4

 

1

 

1

 

1

 

0

 

0

1

0

0

1

n3

n2

n1

n0

1C90H–1C9FH

 

 

 

 

DEC [%Y]+,n4

 

1

 

1

 

1

 

0

 

0

1

0

1

1

n3

n2

n1

n0

1CB0H–1CBFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

 

E

 

I

 

C

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

↓

 

–

 

↕

 

 

↕

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode:

Src: Immediate data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dst: Register indirect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended addressing: Invalid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B.

S1C63000 CORE CPU MANUAL

EPSON

89