CHAPTER 4: INSTRUCTION SET

RETS

 

 

 

Return and skip

 

 

 

 

 

 

 

 

 

 

2 cycles

Function: PC ←

([SP1*4+3]~[SP1*4]), SP1 ←

 

SP1 +1, PC ←

PC + 1

 

 

 

 

 

 

 

After executing the RET instruction, increments the PC to skip 1 instruction immediately after

 

the return.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Code:

Mnemonic

MSB

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

 

RETS

 

1

 

1

1

 

1

1

1

1

1

1

1

0

1

 

1

1FFBH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

E

 

I

C

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL %r

Rotate left r reg. with carry

1 cycle

Function: C 3 2 1 0 r

Rotates the content of the r register (A or B) including the carry (C) to the left for 1 bit. The content of the C flag moves to bit 0 of the r register and bit 3 moves to the C flag.

Code:

Mnemonic

 

 

MSB

 

 

 

 

 

 

 

 

 

 

LSB

 

 

RL %A

 

 

 

1

 

0

0

0

0

1

1

1

1

0

0

1

 

0

10F2H

 

RL %B

 

 

 

1

 

0

0

0

0

1

1

1

1

0

1

1

 

0

10F6H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

E

 

I

 

C

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode:

Register direct

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended addressing: Invalid

 

 

 

 

 

 

 

 

 

 

 

 

120

EPSON

S1C63000 CORE CPU MANUAL