Epson S1C63000 60

CHAPTER 4: INSTRUCTION SET

	Mnemonic					Machine code										Operation	Cycle		Flag			EXT.	Page
	Mnemonic	12	11	10	9		8	7	6	5	4	3	2	1	0	Operation	Cycle	E	I	C	Z	mode	Page
SLL	[%X]	1	0	0	0	0		1	1	1	0	0	0	0	0	[X] (C←D3←D2←D1←D0←0)	2	↓	–↔ ↔			●	132
	[%X]+	1	0	0	0	0		1	1	1	0	0	0	0	1	[X] (C←D3←D2←D1←D0←0), X ← X+1	2	↓	–↔ ↔			⋅	132
	[%Y]	1	0	0	0	0		1	1	1	0	0	0	1	0	[Y] (C←D3←D2←D1←D0←0)	2	↓	–↔ ↔			●	132
	[%Y]+	1	0	0	0	0		1	1	1	0	0	0	1	1	[Y] (C←D3←D2←D1←D0←0), Y ← Y+1	2	↓	–↔ ↔			⋅	132
SLP		1	1	1	1	1		1	1	1	1	1	1	0	1	Sleep	2	↓	–	– –		⋅	133
SRL	%A	1	0	0	0	0		1	1	1	1	0	0	0	1	A (0→D3→D2→D1→D0→C)	1	↓	–↔ ↔			⋅	133
	%B	1	0	0	0	0		1	1	1	1	0	1	0	1	B (0→D3→D2→D1→D0→C)	1	↓	–↔ ↔			⋅	133
	[%X]	1	0	0	0	0		1	1	1	0	0	1	0	0	[X] (0→D3→D2→D1→D0→C)	2	↓	–↔ ↔			●	134
	[%X]+	1	0	0	0	0		1	1	1	0	0	1	0	1	[X] (0→D3→D2→D1→D0→C), X ← X+1	2	↓	–↔ ↔			⋅	134
	[%Y]	1	0	0	0	0		1	1	1	0	0	1	1	0	[Y] (0→D3→D2→D1→D0→C)	2	↓	–↔ ↔			●	134
	[%Y]+	1	0	0	0	0		1	1	1	0	0	1	1	1	[Y] (0→D3→D2→D1→D0→C), Y ← Y+1	2	↓	–↔ ↔			⋅	134
SUB	%A,%A	1	1	0	0	0		0	1	1	1	0	0	0	X	A ← A-A	1	↓	– ↓ ↑			⋅	135
	%A,%B	1	1	0	0	0		0	1	1	1	0	0	1	X	A ← A-B	1	↓	–↔ ↔			⋅	135
	%A,imm4	1	1	0	0	0		0	1	0	0	i3 i2 i1 i0				A ← A-imm4	1	↓	–↔ ↔			⋅	135
	%A,[%X]	1	1	0	0	0		0	1	1	0	0	0	0	0	A ← A-[X]	1	↓	–↔ ↔			●	136
	%A,[%X]+	1	1	0	0	0		0	1	1	0	0	0	0	1	A ← A-[X], X ← X+1	1	↓	–↔ ↔			⋅	136
	%A,[%Y]	1	1	0	0	0		0	1	1	0	0	0	1	0	A ← A-[Y]	1	↓	–↔ ↔			●	136
	%A,[%Y]+	1	1	0	0	0		0	1	1	0	0	0	1	1	A ← A-[Y], Y ← Y+1	1	↓	–↔ ↔			⋅	136
	%B,%A	1	1	0	0	0		0	1	1	1	0	1	0	X	B ← B-A	1	↓	–↔ ↔			⋅	135
	%B,%B	1	1	0	0	0		0	1	1	1	0	1	1	X	B ← B-B	1	↓	– ↓ ↑			⋅	135
	%B,imm4	1	1	0	0	0		0	1	0	1	i3 i2 i1 i0				B ← B-imm4	1	↓	–↔ ↔			⋅	135
	%B,[%X]	1	1	0	0	0		0	1	1	0	0	1	0	0	B ← B-[X]	1	↓	–↔ ↔			●	136
	%B,[%X]+	1	1	0	0	0		0	1	1	0	0	1	0	1	B ← B-[X], X ← X+1	1	↓	–↔ ↔			⋅	136
	%B,[%Y]	1	1	0	0	0		0	1	1	0	0	1	1	0	B ← B-[Y]	1	↓	–↔ ↔			●	136
	%B,[%Y]+	1	1	0	0	0		0	1	1	0	0	1	1	1	B ← B-[Y], Y ← Y+1	1	↓	–↔ ↔			⋅	136
	[%X],%A	1	1	0	0	0		0	1	1	0	1	0	0	0	[X] ← [X]-A	2	↓	–↔ ↔			●	137
	[%X],%B	1	1	0	0	0		0	1	1	0	1	1	0	0	[X] ← [X]-B	2	↓	–↔ ↔			●	137
	[%X],imm4	1	1	0	0	0		0	0	0	0	i3 i2 i1 i0				[X] ← [X]-imm4	2	↓	–↔ ↔			●	138
	[%X]+,%A	1	1	0	0	0		0	1	1	0	1	0	0	1	[X] ← [X]-A, X ← X+1	2	↓	–↔ ↔			⋅	137
	[%X]+,%B	1	1	0	0	0		0	1	1	0	1	1	0	1	[X] ← [X]-B, X ← X+1	2	↓	–↔ ↔			⋅	137
	[%X]+,imm4	1	1	0	0	0		0	0	0	1	i3 i2 i1 i0				[X] ← [X]-imm4, X ← X+1	2	↓	–↔ ↔			⋅	138
	[%Y],%A	1	1	0	0	0		0	1	1	0	1	0	1	0	[Y] ← [Y]-A	2	↓	–↔ ↔			●	137
	[%Y],%B	1	1	0	0	0		0	1	1	0	1	1	1	0	[Y] ← [Y]-B	2	↓	–↔ ↔			●	137
	[%Y],imm4	1	1	0	0	0		0	0	1	0	i3 i2 i1 i0				[Y] ← [Y]-imm4	2	↓	–↔ ↔			●	138
	[%Y]+,%A	1	1	0	0	0		0	1	1	0	1	0	1	1	[Y] ← [Y]-A, Y ← Y+1	2	↓	–↔ ↔			⋅	137
	[%Y]+,%B	1	1	0	0	0		0	1	1	0	1	1	1	1	[Y] ← [Y]-B, Y ← Y+1	2	↓	–↔ ↔			⋅	137
	[%Y]+,imm4	1	1	0	0	0		0	0	1	1	i3 i2 i1 i0				[Y] ← [Y]-imm4, Y ← Y+1	2	↓	–↔ ↔			⋅	138
TST	[00addr6],imm2	1	0	0	1	0		i1 i0 a5 a4				a3 a2 a1 a0				[00addr6]∧(2imm2)	1	↓	–	–↔		⋅	139
	[FFaddr6],imm2	1	0	0	1	1		i1 i0 a5 a4				a3 a2 a1 a0				[FFaddr6]∧(2imm2)	1	↓	–	–↔		⋅	139
XOR	%A,%A	1	1	0	1	1		1	1	1	1	0	0	0	X	A ← A∀A	1	↓	–	– ↑		⋅	139
	%A,%B	1	1	0	1	1		1	1	1	1	0	0	1	X	A ← A∀B	1	↓	–	–↔		⋅	139
	%A,imm4	1	1	0	1	1		1	1	0	0	i3 i2 i1 i0				A ← A∀imm4	1	↓	–	–↔		⋅	140
	%A,[%X]	1	1	0	1	1		1	1	1	0	0	0	0	0	A ← A∀[X]	1	↓	–	–↔		●	141
	%A,[%X]+	1	1	0	1	1		1	1	1	0	0	0	0	1	A ← A∀[X], X ← X+1	1	↓	–	–↔		⋅	141
	%A,[%Y]	1	1	0	1	1		1	1	1	0	0	0	1	0	A ← A∀[Y]	1	↓	–	–↔		●	141
	%A,[%Y]+	1	1	0	1	1		1	1	1	0	0	0	1	1	A ← A∀[Y], Y ← Y+1	1	↓	–	–↔		⋅	141
	%B,%A	1	1	0	1	1		1	1	1	1	0	1	0	X	B ← B∀A	1	↓	–	–↔		⋅	139
	%B,%B	1	1	0	1	1		1	1	1	1	0	1	1	X	B ← B∀B	1	↓	–	– ↑		⋅	139
	%B,imm4	1	1	0	1	1		1	1	0	1	i3 i2 i1 i0				B ← B∀imm4	1	↓	–	–↔		⋅	140
	%B,[%X]	1	1	0	1	1		1	1	1	0	0	1	0	0	B ← B∀[X]	1	↓	–	–↔		●	141
	%B,[%X]+	1	1	0	1	1		1	1	1	0	0	1	0	1	B ← B∀[X], X ← X+1	1	↓	–	–↔		⋅	141
	%B,[%Y]	1	1	0	1	1		1	1	1	0	0	1	1	0	B ← B∀[Y]	1	↓	–	–↔		●	141
	%B,[%Y]+	1	1	0	1	1		1	1	1	0	0	1	1	1	B ← B∀[Y], Y ← Y+1	1	↓	–	–↔		⋅	141
	%F,imm4	1	0	0	0	0		1	0	1	0	i3 i2 i1 i0				F ← F∀imm4	1	↔ ↔ ↔ ↔				⋅	140
	[%X],%A	1	1	0	1	1		1	1	1	0	1	0	0	0	[X] ← [X]∀A	2	↓ –		–↔		●	142
	[%X],%B	1	1	0	1	1		1	1	1	0	1	1	0	0	[X] ← [X]∀B	2	↓ –		–↔		●	142
	[%X],imm4	1	1	0	1	1		1	0	0	0	i3 i2 i1 i0				[X] ← [X]∀imm4	2	↓ –		–↔		●	143
	[%X]+,%A	1	1	0	1	1		1	1	1	0	1	0	0	1	[X] ← [X]∀A, X ← X+1	2	↓ –		–↔		⋅	142
	[%X]+,%B	1	1	0	1	1		1	1	1	0	1	1	0	1	[X] ← [X]∀B, X ← X+1	2	↓ –		–↔		⋅	142
	[%X]+,imm4	1	1	0	1	1		1	0	0	1	i3 i2 i1 i0				[X] ← [X]∀imm4, X ← X+1	2	↓ –		–↔		⋅	143
	[%Y],%A	1	1	0	1	1		1	1	1	0	1	0	1	0	[Y] ← [Y]∀A	2	↓ –		–↔		●	142
	[%Y],%B	1	1	0	1	1		1	1	1	0	1	1	1	0	[Y] ← [Y]∀B	2	↓ –		–↔		●	142
	[%Y],imm4	1	1	0	1	1		1	0	1	0	i3 i2 i1 i0				[Y] ← [Y]∀imm4	2	↓ –		–↔		●	143
	[%Y]+,%A	1	1	0	1	1		1	1	1	0	1	0	1	1	[Y] ← [Y]∀A, Y ← Y+1	2	↓ –		–↔		⋅	142
	[%Y]+,%B	1	1	0	1	1		1	1	1	0	1	1	1	1	[Y] ← [Y]∀B, Y ← Y+1	2	↓ –		–↔		⋅	142
	[%Y]+,imm4	1	1	0	1	1		1	0	1	1	i3 i2 i1 i0				[Y] ← [Y]∀imm4, Y ← Y+1	2	↓ –		–↔		⋅	143

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S1C63000 CORE CPU MANUAL