Epson S1C63000 8/16-bitoperation, ALU shift and rotate operation

CHAPTER 4: INSTRUCTION SET

ALU shift and rotate operation

	Mnemonic					Machine code										Operation	Cycle		Flag			EXT.	Page
		12	11	10	9		8	7	6	5	4	3	2	1	0			E	I	C	Z	mode
SLL	%A	1	0	0	0	0		1	1	1	1	0	0	0	0	A (C←D3←D2←D1←D0←0)	1	↓ –↔ ↔				⋅	131
	%B	1	0	0	0	0		1	1	1	1	0	1	0	0	B (C←D3←D2←D1←D0←0)	1	↓ –↔ ↔				⋅	131
	[%X]	1	0	0	0	0		1	1	1	0	0	0	0	0	[X] (C←D3←D2←D1←D0←0)	2	↓ –↔ ↔				●	132
	[%X]+	1	0	0	0	0		1	1	1	0	0	0	0	1	[X] (C←D3←D2←D1←D0←0), X ← X+1	2	↓ –↔ ↔				⋅	132
	[%Y]	1	0	0	0	0		1	1	1	0	0	0	1	0	[Y] (C←D3←D2←D1←D0←0)	2	↓ –↔ ↔				●	132
	[%Y]+	1	0	0	0	0		1	1	1	0	0	0	1	1	[Y] (C←D3←D2←D1←D0←0), Y ← Y+1	2	↓ –↔ ↔				⋅	132
SRL	%A	1	0	0	0	0		1	1	1	1	0	0	0	1	A (0→D3→D2→D1→D0→C)	1	↓ –↔ ↔				⋅	133
	%B	1	0	0	0	0		1	1	1	1	0	1	0	1	B (0→D3→D2→D1→D0→C)	1	↓ –↔ ↔				⋅	133
	[%X]	1	0	0	0	0		1	1	1	0	0	1	0	0	[X] (0→D3→D2→D1→D0→C)	2	↓ –↔ ↔				●	134
	[%X]+	1	0	0	0	0		1	1	1	0	0	1	0	1	[X] (0→D3→D2→D1→D0→C), X ← X+1	2	↓ –↔ ↔				⋅	134
	[%Y]	1	0	0	0	0		1	1	1	0	0	1	1	0	[Y] (0→D3→D2→D1→D0→C)	2	↓ –↔ ↔				●	134
	[%Y]+	1	0	0	0	0		1	1	1	0	0	1	1	1	[Y] (0→D3→D2→D1→D0→C), Y ← Y+1	2	↓ –↔ ↔				⋅	134
RL	%A	1	0	0	0	0		1	1	1	1	0	0	1	0	A (C←D3←D2←D1←D0←C)	1	↓ –↔ ↔				⋅	120
	%B	1	0	0	0	0		1	1	1	1	0	1	1	0	B (C←D3←D2←D1←D0←C)	1	↓ –↔ ↔				⋅	120
	[%X]	1	0	0	0	0		1	1	1	0	1	0	0	0	[X] (C←D3←D2←D1←D0←C)	2	↓ –↔ ↔				●	121
	[%X]+	1	0	0	0	0		1	1	1	0	1	0	0	1	[X] (C←D3←D2←D1←D0←C), X ← X+1	2	↓ –↔ ↔				⋅	121
	[%Y]	1	0	0	0	0		1	1	1	0	1	0	1	0	[Y] (C←D3←D2←D1←D0←C)	2	↓ –↔ ↔				●	121
	[%Y]+	1	0	0	0	0		1	1	1	0	1	0	1	1	[Y] (C←D3←D2←D1←D0←C), Y ← Y+1	2	↓ –↔ ↔				⋅	121
RR	%A	1	0	0	0	0		1	1	1	1	0	0	1	1	A (C→D3→D2→D1→D0→C)	1	↓ –↔ ↔				⋅	122
	%B	1	0	0	0	0		1	1	1	1	0	1	1	1	B (C→D3→D2→D1→D0→C)	1	↓ –↔ ↔				⋅	122
	[%X]	1	0	0	0	0		1	1	1	0	1	1	0	0	[X] (C→D3→D2→D1→D0→C)	2	↓ –↔ ↔				●	122
	[%X]+	1	0	0	0	0		1	1	1	0	1	1	0	1	[X] (C→D3→D2→D1→D0→C), X ← X+1	2	↓ –↔ ↔				⋅	123
	[%Y]	1	0	0	0	0		1	1	1	0	1	1	1	0	[Y] (C→D3→D2→D1→D0→C)	2	↓ –↔ ↔				●	122
	[%Y]+	1	0	0	0	0		1	1	1	0	1	1	1	1	[Y] (C→D3→D2→D1→D0→C), Y ← Y+1	2	↓ –↔ ↔				⋅	123

8/16-bit operation

	Mnemonic					Machine code										Operation	Cycle		Flag			EXT.	Page
		12	11	10	9		8	7	6	5	4	3	2	1	0			E	I	C	Z	mode
LDB	%BA,%XL	1	1	1	1	1		1	1	0	0	1	0	0	0	BA ← XL	1	↓ – – –				⋅	107
	%BA,%XH	1	1	1	1	1		1	1	0	0	1	0	0	1	BA ← XH	1	↓ – – –				⋅	107
	%BA,%YL	1	1	1	1	1		1	1	0	0	1	0	1	0	BA ← YL	1	↓ – – –				⋅	107
	%BA,%YH	1	1	1	1	1		1	1	0	0	1	0	1	1	BA ← YH	1	↓ – – –				⋅	107
	%BA,%EXT	1	1	1	1	1		1	1	0	1	0	1	1	X	BA ← EXT	1	↓ – – –				⋅	106
	%BA,%SP1	1	1	1	1	1		1	1	0	0	1	1	0	X	BA ← SP1	1	↓ – – –				⋅	107
	%BA,%SP2	1	1	1	1	1		1	1	0	0	1	1	1	X	BA ← SP2	1	↓ – – –				⋅	107
	%BA,imm8	0	1	0	0	1		i7 i6 i5 i4				i3 i2 i1 i0				BA ← imm8	1	↓ – – –				⋅	105
	%BA,[%X]+	1	1	1	1	1		1	1	0	1	1	0	0	0	A ← [X], B ← [X+1], X ← X+2	2	↓ – – –				⋅	106
	%BA,[%Y]+	1	1	1	1	1		1	1	0	1	1	0	1	0	A ← [Y], B ← [Y+1], Y ← Y+2	2	↓ – – –				⋅	106
LDB	%XL,%BA	1	1	1	1	1		1	1	0	0	0	0	0	0	XL ← BA	1	↓ – – –				⋅	110
	%XL,imm8	0	1	0	1	0		i7 i6 i5 i4				i3 i2 i1 i0				XL ← imm8	1	↓ – – –				●	110
	%XH,%BA	1	1	1	1	1		1	1	0	0	0	0	0	1	XH ← BA	1	↓ – – –				⋅	110
LDB	%YL,%BA	1	1	1	1	1		1	1	0	0	0	0	1	0	YL ← BA	1	↓ – – –				⋅	110
	%YL,imm8	0	1	0	1	1		i7 i6 i5 i4				i3 i2 i1 i0				YL ← imm8	1	↓ – – –				●	110
	%YH,%BA	1	1	1	1	1		1	1	0	0	0	0	1	1	YH ← BA	1	↓ – – –				⋅	110
LDB	%EXT,%BA	1	1	1	1	1		1	1	0	1	0	1	0	X	EXT ← BA	1	↑ – – –				⋅	109
	%EXT,imm8	0	1	0	0	0		i7 i6 i5 i4				i3 i2 i1 i0				EXT ← imm8	1	↑ – – –				⋅	109
LDB	%SP1,%BA	1	1	1	1	1		1	1	0	0	0	1	0	X	SP1 ← BA	1	↓ – – –				⋅	111
	%SP2,%BA	1	1	1	1	1		1	1	0	0	0	1	1	X	SP2 ← BA	1	↓ – – –				⋅	111
LDB	[%X]+,%BA	1	1	1	1	1		1	1	0	1	1	0	0	1	[X] ← A, [X+1] ← B, X ← X+2	2	↓ – – –				⋅	108
	[%X]+,imm8	0	0	0	0	1		i7 i6 i5 i4				i3 i2 i1 i0				[X] ← i3~0, [X+1] ← i7~4, X ← X+2	2	↓ – – –				⋅	108
LDB	[%Y]+,%BA	1	1	1	1	1		1	1	0	1	1	0	1	1	[Y] ← A, [Y+1] ← B, Y ← Y+2	2	↓ – – –				⋅	108
ADD	%X,%BA	1	1	1	1	1		1	1	0	1	0	0	0	X	X ← X+BA	1	↓ – –↔				⋅	72
	%X,sign8	0	1	1	0	0		s7 s6 s5 s4				s3 s2 s1 s0				X ← X+sign8 (sign8=-128~127)	1	↓ – –↔				●	72
	%Y,%BA	1	1	1	1	1		1	1	0	1	0	0	1	X	Y ← Y+BA	1	↓ – –↔				⋅	72
	%Y,sign8	0	1	1	0	1		s7 s6 s5 s4				s3 s2 s1 s0				Y ← Y+sign8 (sign8=-128~127)	1	↓ – –↔				●	72
CMP	%X,imm8	0	1	1	1	0		[	FFH - imm8						]	X-imm8 (imm8=0~255)	1	↓ –↔ ↔				●	88
	%Y,imm8	0	1	1	1	1		[	FFH - imm8						]	Y-imm8 (imm8=0~255)	1	↓ –↔ ↔				●	88
INC	%SP1	1	1	1	1	1		1	1	1	0	1	0	0	0	SP1 ← SP1+1	1	↓ – –↔				⋅	94
	%SP2	1	1	1	1	1		1	1	1	0	1	1	0	0	SP2 ← SP2+1	1	↓ – –↔				⋅	94
DEC	%SP1	1	1	1	1	1		1	1	1	0	0	0	0	0	SP1 ← SP1-1	1	↓ – –↔				⋅	90
	%SP2	1	1	1	1	1		1	1	1	0	0	1	0	0	SP2 ← SP2-1	1	↓ – –↔				⋅	90

46 EPSON S1C63000 CORE CPU MANUAL