Epson S1C63000 EX %r,[%ir], EX %r,[%ir]+, Code:, Mode:, Code:, Mode:, Flags:, Flags:, 2 cycles, Extended, 2 cycles, Function: r ↔, operation: EX, Function: r ↔

																					CHAPTER 4: INSTRUCTION SET
EX %r,[%ir]					Exchange r reg. and location [ir reg.]																	2 cycles
Function: r ↔		[ir]
	Exchanges the contents of the r register (A or B) and data memory addressed by the ir register
	(X or Y).
Code:	Mnemonic				MSB															LSB
	EX %A,[%X]					1		0		0	0	0	1	1	1	1	1	0	0		0	10F8H
	EX %A,[%Y]					1		0		0	0	0	1	1	1	1	1	0	1		0	10FAH
	EX %B,[%X]					1		0		0	0	0	1	1	1	1	1	1	0		0	10FCH
	EX %B,[%Y]					1		0		0	0	0	1	1	1	1	1	1	1		0	10FEH
Flags:	E			I	C		Z
	↓			–	–		–
Mode:	Src: Register indirect
	Dst: Register direct
	Extended addressing: Valid
Extended	LDB			%EXT,imm8
operation: EX			%r,[%X]			r ↔			[00imm8] (00imm8 = 0000H + 00H to FFH)
	LDB			%EXT,imm8
	EX		%r,[%Y]			r ↔			[FFimm8] (FFimm8 = FF00H + 00H to FFH)

EX %r,[%ir]+				Exchange r reg. and location [ir reg.] and increment ir reg.																	2 cycles
Function: r ↔		[ir], ir ← ir + 1
	Exchanges the contents of the r register (A or B) and data memory addressed by the ir register
	(X or Y). Then increments the ir register (X or Y). The increment result of the ir register does not
	affect the flags.
Code:	Mnemonic			MSB														LSB
	EX %A,[%X]+				1		0	0	0	0	1	1	1	1	1	0	0		1	10F9H
	EX %A,[%Y]+				1		0	0	0	0	1	1	1	1	1	0	1		1	10FBH
	EX %B,[%X]+				1		0	0	0	0	1	1	1	1	1	1	0		1	10FDH
	EX %B,[%Y]+				1		0	0	0	0	1	1	1	1	1	1	1		1	10FFH
Flags:	E		I	C		Z
	↓		–	–		–
Mode:	Src: Register indirect
	Dst: Register direct
	Extended addressing: Invalid

S1C63000 CORE CPU MANUAL EPSON 91