Epson S1C63000 BIT [%ir],imm4, BIT [%ir]+,imm4, 1 cycle, Test bit of location [ir reg.] with immediate data imm4

CHAPTER 4: INSTRUCTION SET

BIT [%ir],imm4

Test bit of location [ir reg.] with immediate data imm4

1 cycle

Function: [ir] ∧

imm4

Performs a logical AND of the 4-bit immediate data imm4 and the content of the data memory

addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is changed due

to the operation result, but the content of the memory is not changed.

Code:

Mnemonic

MSB

LSB

BIT [%X],imm4

1

1

0

1

0

1

0

0

0

i3

i2

i1

i0

1A80H–1A8FH

BIT [%Y],imm4

1

1

0

1

0

1

0

1

0

i3

i2

i1

i0

1AA0H–1AAFH

Flags:

E

I

C

Z

↓

–

–

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Valid

Extended

LDB

%EXT,imm8

operation: BIT

[%X],imm4

[00imm8] ∧

imm4 (00imm8 = 0000H + 00H to FFH)

LDB

%EXT,imm8

BIT

[%Y],imm4

[FFimm8] ∧

imm4 (FFimm8 = FF00H + 00H to FFH)

BIT [%ir]+,imm4

Test bit of location [ir reg.] with immediate data imm4 and increment ir reg. 1 cycle

Function: [ir] ∧

imm4, ir ←

ir + 1

Performs a logical AND of the 4-bit immediate data imm4 and the content of the data memory

addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is changed due

to the operation result, but the content of the memory is not changed. Then increments the ir

register (X or Y). The increment result of the ir register does not affect the flags.

Code:

Mnemonic

MSB

LSB

BIT [%X]+,imm4

1

1

0

1

0

1

0

0

1

i3

i2

i1

i0

1A90H–1A9FH

BIT [%Y]+,imm4

1

1

0

1

0

1

0

1

1

i3

i2

i1

i0

1AB0H–1ABFH

Flags:

E

I

C

Z

↓

–

–

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Invalid

S1C63000 CORE CPU MANUAL EPSON 81