CHAPTER 4: INSTRUCTION SET

LDB [%ir]+,%BA

Load BA reg. into location [ir reg.] and increment ir reg.

2 cycles

Function: [ir] ←

A, [ir + 1] ←

B, ir ←

ir + 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Loads the content of the BA register into the data memory. The content of the A register is

 

loaded into the data memory addressed by the ir register (X or Y) as the low-order 4 bits, and

 

the content of the B register is loaded into the next address as the high-order 4 bits. The ir

 

register (X or Y) is incremented by 2 words.

 

 

 

 

 

 

 

 

 

 

Code:

Mnemonic

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

 

 

LDB [%X]+,%BA

 

1

 

1

1

 

1

1

1

1

0

1

1

0

0

 

1

1FD9H

 

 

 

LDB [%Y]+,%BA

 

1

 

1

1

 

1

1

1

1

0

1

1

0

1

 

1

1FDBH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

E

 

I

C

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

↓

 

–

–

 

–

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode:

Src: Register direct

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dst: Register indirect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended addressing: Invalid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDB [%X]+,imm8

Load immediate data imm8 into location [X reg.] and increment X reg. 2 cycles
Function: [X] ←

i3-0, [X+1] ←

i7-4, X ←

X + 2

 

Loads the 8-bit immediate data imm8 into the data memory. The low-order 4 bit-data is loaded

 

into the data memory addressed by the ir register (X or Y), and the high-order 4-bit data is

 

loaded into the next address. The ir register (X or Y) is incremented by 2 words.

Code:

Mnemonic

 

MSB

 

 

 

 

 

 

 

 

 

LSB

 

LDB

[%X]+,imm8

 

0

0

0

0

1

i7

i6

i5

i4

i3

i2

i1

i0

0100H–01FFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flags:

E

 

I

C

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

↓

 

–

–

 

–

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode:

Src: Immediate data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dst: Register indirect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended addressing: Invalid

108

EPSON

S1C63000 CORE CPU MANUAL