Epson S1C63000 ADD %r,[%ir]+, ADD [%ir],%r, 1 cycle, 2 cycles, Add r reg. to location [ir reg.], Add location [ir reg.] to r reg. and increment ir reg

CHAPTER 4: INSTRUCTION SET

ADD %r,[%ir]+				Add location [ir reg.] to r reg. and increment ir reg.																		1 cycle
Function: r ←		r + [ir], ir ←		ir + 1
	Adds the content of the data memory addressed by the ir register (X or Y) to the r register (A or
	B). Then increments the ir register (X or Y). The flags change due to the operation result of the r
	register and the increment result of the ir register does not affect the flags.
Code:	Mnemonic				MSB														LSB
	ADD %A,[%X]+					1		1	0	0	1	0	1	1	0	0	0	0		1	1961H
	ADD %A,[%Y]+					1		1	0	0	1	0	1	1	0	0	0	1		1	1963H
	ADD %B,[%X]+					1		1	0	0	1	0	1	1	0	0	1	0		1	1965H
	ADD %B,[%Y]+					1		1	0	0	1	0	1	1	0	0	1	1		1	1967H
Flags:	E		I	C			Z
	↓		–	↕				↕
Mode:	Src: Register indirect
	Dst: Register direct
	Extended addressing: Invalid

ADD [%ir],%r				Add r reg. to location [ir reg.]																2 cycles
Function: [ir] ←		[ir] + r
	Adds the content of the r register (A or B) to the data memory addressed by the ir register (X or
	Y).
Code:	Mnemonic			MSB														LSB
	ADD [%X],%A				1		1	0	0	1	0	1	1	0	1	0	0		0	1968H
	ADD [%X],%B				1		1	0	0	1	0	1	1	0	1	1	0		0	196CH
	ADD [%Y],%A				1		1	0	0	1	0	1	1	0	1	0	1		0	196AH
	ADD [%Y],%B				1		1	0	0	1	0	1	1	0	1	1	1		0	196EH
Flags:	E		I	C		Z
	↓		–	↕			↕
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Valid
Extended	LDB		%EXT,imm8
operation: ADD			[%X],%r		[00imm8] ←					[00imm8] + r (00imm8 = 0000H + 00H to FFH)
	LDB		%EXT,imm8
	ADD	[%Y],%r			[FFimm8] ←					[FFimm8] + r (FFimm8 = FF00H + 00H to FFH)

70 EPSON S1C63000 CORE CPU MANUAL