Epson S1C63000 CMP [%ir],imm4, CMP [%ir]+,imm4, 1 cycle, Compare location [ir reg.] with immediate data imm4

CHAPTER 4: INSTRUCTION SET

CMP [%ir],imm4 Compare location [ir reg.] with immediate data imm4 1 cycle

Function: [ir] - imm4

Subtracts the 4-bit immediate data imm4 from the content of the data memory addressed by the ir register (X or Y). It changes the flags (Z and C), but does not change the content of the memory.

Code:

Mnemonic

MSB

LSB

CMP [%X],imm4

1

1

1

1

0

0

0

0

0

i3

i2

i1

i0

1E00H–1E0FH

CMP [%Y],imm4

1

1

1

1

0

0

0

1

0

i3

i2

i1

i0

1E20H–1E2FH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Valid

Extended

LDB

%EXT,imm8

operation: CMP

[%X],imm4

[00imm8] - imm4 (00imm8 = 0000H + 00H to FFH)

LDB

%EXT,imm8

CMP

[%Y],imm4

[FFimm8] - imm4 (FFimm8 = FF00H + 00H to FFH)

CMP [%ir]+,imm4

Compare location [ir reg.] with immediate data imm4 and increment ir reg. 1 cycle

Function: [ir] - imm4, ir ←

ir + 1

Subtracts the 4-bit immediate data imm4 from the content of the data memory addressed by

the ir register (X or Y). It changes the flags (Z and C), but does not change the content of the

memory. Then increments the ir register (X or Y). The increment result of the ir register does

not affect the flags.

Code:

Mnemonic

MSB

LSB

CMP [%X]+,imm4

1

1

1

1

0

0

0

0

1

i3

i2

i1

i0

1E10H–1E1FH

CMP [%Y]+,imm4

1

1

1

1

0

0

0

1

1

i3

i2

i1

i0

1E30H–1E3FH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Invalid

S1C63000 CORE CPU MANUAL EPSON 87