CHAPTER 2: ARCHITECTURE

The SP1 increment/decrement affects only the 8-bit field shown in Figure 2.3.3.1, and its operation is performed cyclically. In other words, if the SP1 is decremented by the PUSH instruction or other conditions when the SP1 is 00H (indicating the memory address 0000H), the SP1 becomes FFH (indicating the memory address 03FCH). Similarly, if the SP1 is incremented by the POP instruction or other conditions when the SP1 is FFH (indicating the memory address 03FCH), the SP1 becomes 00H (indicating the memory address 0000H).

•Queue register

The queue register is provided in order to reduce the process time of the 16-bit data transfer by the SP1. The queue register retains 16-bit data in the RAM indicated with the SP1. It is accessed when the following instructions are executed, not by programs directly.

1.When the call instruction or the PUSH instruction is executed, and when an interrupt is generated

When the CALR or CALZ instruction is executed, a software interrupt by the INT instruction is generated, and a hardware interrupt is generated, the PC value for returning is written in the memory [SP1-1]. When the "PUSH %X" or "PUSH %Y" instruction is executed, the content of the X register or Y register is written in the memory [SP1-1]. At this time, the same data which is written in the memory [SP1-1] is also written to the queue register.

2.When the return instruction or the POP instruction is executed

When the RET, RETS, RETD, RETI, "POP %X" or "POP %Y" instructions are executed, the data retained in the queue register is returned to the PC, X register or Y register. Since the SP1 is incremented, the content of the queue register is renewed (it generates a bus cycle to load the content of the memory [SP1+1] to the queue register).

3.When the "LDB %SP1, %BA", "INC SP1" or "DEC SP1" instructions are executed

When these instructions are executed, the content of the queue register is also renewed (it generates a bus cycle to load the content of the memory [SP1] to the queue register).

Note: As shown above, the memory content that is indicated by the SP1 is written to the queue register according to the SP1 changes. Therefore, the queue register is not renewed even if the memory [SP1] is directly modified when the SP1 is not changed. Be aware that intended return and POP operations cannot be performed if such an operation is done.

(2)Stack pointer SP2

The SP2 is used for the normal 4-bit data stack.

D15

D8 D7

 

D0

00H

 

7

SP2

0

Stack pointer 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8 bits to be modified

Fig. 2.3.3.3 SP2 configuration

In the case of the SP1, the D8–D15 within the 16 bits are fixed at "0". 8 bits of the D0–D7 can be set by software. Furthermore, the hardware also operates for this 8-bit field. The address range that can be used for the data stack is limited to within 0000H to 00FFH. Data evacuation/return is done in 1-word units.

This stack is used to evacuate the F register data when an interrupt is generated. It is also used when the 4-bit register data (A, B, F) is evacuated using the PUSH instruction. The register data is written into the stack as shown in Figure 2.3.3.4.

The SP2 is decremented after the data is evacuated and is incremented when the data is returned.

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EPSON

S1C63000 CORE CPU MANUAL