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Epson S1C63000 SLL [%ir], SLL [%ir]+, Code:, Mode:, Code:, Mode:, Flags:, Flags:, 2 cycles, Extended, 2 cycles, Function:, Function: C, operation: SLL

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CHAPTER 4: INSTRUCTION SET

SLL [%ir]									Shift left location [ir reg.] logical	2 cycles
Function: C									0 [ir]
			3	2	1	0

Shifts the content of the data memory addressed by the ir register (X or Y) to the left for 1 bit. Bit 3 of the r register moves to the C flag and bit 0 goes "0".

Code:	Mnemonic				MSB																	LSB
	SLL [%X]					1		0	0	0	0	1		1		1	0	0		0	0		0	10E0H
	SLL [%Y]					1		0	0	0	0	1		1		1	0	0		0	1		0	10E2H

Flags:	E	I		C			Z
	↓	–		↕				↕
Mode:	Register indirect
	Extended addressing: Valid
Extended	LDB	%EXT,imm8
operation: SLL		[%X]				Shifts the content of									[00imm8]				(00imm8 = 0000H + 00H to FFH)
	LDB	%EXT,imm8
	SLL	[%Y]				Shifts the content of [FFimm8] (FFimm8 = FF00H + 00H to FFH)


SLL [%ir]+										Shift left location [ir reg.] logical and increment ir reg.																				2 cycles
Function:	C									0 [ir] , ir ←				ir + 1
			3	2	1		0
			3	2	1		0
	Shifts the content of the data memory addressed by the ir register (X or Y) to the left for 1 bit.
	Bit 3 of the r register moves to the C flag and bit 0 goes "0". Then increments the ir register (X
	or Y). The increment result of the ir register does not affect the flags.
Code:	Mnemonic									MSB																LSB
	SLL [%X]+										1		0		0		0	0	1	1	1	0	0	0	0		1		10E1H
	SLL [%Y]+										1		0		0		0	0	1	1	1	0	0	0	1		1		10E3H

Flags:	E					I				C		Z
	↓					–				↕			↕
Mode:	Register indirect
	Extended addressing: Invalid

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EPSON

S1C63000 CORE CPU MANUAL

Contents

Page © SEIKO EPSON CORPORATION 2001 All rights reserved SEIKO EPSON CORPORATION The information of the product number change Configuration of product number Devices Development tools Comparison table between new and previous number Page S1C63000 CORE CPU MANUAL PREFACE CONTENTS CHAPTER 4 INSTRUCTION SET CHAPTER 1 OUTLINE 1.1 Features 1.2 Instruction Set Features 1.3 Block Diagram 1.4 Input-OutputSignals Table 1.4.1(b) Input/output signal list (2) Data bus I00–I12 Instruction bus Inputs an instruction code CHAPTER 2 ARCHITECTURE 2.1 ALU and Registers 2.1.1 ALU 2.1.2 Register configuration •A and B registers 2.1.3 Flags •Z (zero) flag •C (carry) flag •I flag •E (extension mode) flag •Flag operations 2.1.4 Arithmetic operations with numbering system •Notes in numbering operations 2.1.5 EXT register and data extension (1)Operation for EXT register and E flag (flag register) (2)Extension with E flag •16-bitdata transfer/arithmetic for the index registers X and Y •Extending branch addresses 2.2 Program Memory 2.2.1 Configuration of program memory 2.2.2 PC (program counter) 2.2.3 Branch instructions •PC relative jump instructions (JR) •Indirect jump instruction (JP) •Absolute call instruction (CALZ) •PC relative call instructions (CALR) Page •Return instructions (RET, RETS, RETD, RETI) •Software interrupt instruction (INT) 2.2.4 Table look-upinstruction 2.3 Data Memory 2.3.1 Configuration of data memory 2.3.2 Addressing for data memory •Accessing for addresses 0000H to 00FFH •Accessing for addresses FF00H to FFFFH (I/O memory area) •Accessing for addresses 0000H to 003FH •Accessing for addresses FFC0H to FFFFH (I/O memory area) 2.3.3 Stack and stack pointer (1)Stack pointer SP1 (2)Stack pointer SP2 (3) Notes for using the stack pointer 2.3.4 Memory mapped I/O CHAPTER 3 CPU OPERATION 3 CPU O 3.1 Timing Generator and Bus Cycle 3.2 Instruction Fetch and Execution 3.3 Data Bus (Data Memory) Control 3.3.1 Data bus status 3.3.2 High-impedancecontrol 3.3.3 Interrupt vector read 3.3.4 Memory write 3.3.5 Memory read 3.4 Initial Reset 3.4.1 Initial reset sequence 3.4.2 Initial setting of internal registers 3.5 Interrupts 3.5.1 Interrupt vectors 3.5.2 Interrupt sequence •Hardware interrupts Page Page •Software interrupts 3.5.3 Notes for interrupt processing 3.6 Standby Status 3.6.1 HALT status 3.6.2 SLEEP status Page CHAPTER 4 INSTRUCTION SET 4.1 Addressing Mode •Types of addressing modes 4.1.1 Basic addressing modes •Immediate data addressing •Register direct addressing •Register indirect addressing •6-bitabsolute addressing •Signed 8-bitPC relative addressing 4.1.2 Extended addressing mode •16-bitimmediate data addressing •8-bitabsolute addressing •Signed 16-bitPC relative addressing 4.2 Instruction List 4.2.1 Function classification 4.2.2 Symbol meanings Register names Immediate data Memory Flags Operations and others Extended addressing mode (EXT.mode) 4.2.3 Instruction list by function ALU alithmetic operation (1/3) ALU alithmetic operation (2/3) ALU alithmetic operation (3/3) ALU logic operation (1/2) ALU logic operation (2/2) ALU shift and rotate operation 8/16-bitoperation Stack operation Branch control System control 4.2.4 List in alphabetical order Page Page Page Page Page Page 4.2.5 List of extended addressing instructions 8-bitabsolute addressing (2/4) 8-bitabsolute addressing (3/4) 8-bitabsolute addressing (4/4) 4.3 Instruction Formats 4.4 Detailed Explanation of Instructions ADC %r,%r ADC %r,imm4 ADC %r,[%ir] ADC %r,[%ir]+ ADC [%ir],%r ADC [%ir]+,%r ADC [%ir],imm4 ADC [%ir]+,imm4 ADC %B,%A,n4 ADC %B,[%ir],n4 ADC %B,[%ir]+,n4 ADC [%ir],%B,n4 ADC [%ir]+,%B,n4 ADC [%ir],0,n4 ADC [%ir]+,0,n4 ADD %r,%r ADD %r,imm4 ADD %r,[%ir] ADD %r,[%ir]+ ADD [%ir],%r ADD [%ir]+,%r ADD [%ir],imm4 ADD [%ir]+,imm4 ADD %ir,%BA ADD %ir,sign8 AND %r,%r AND %r,imm4 AND %F,imm4 AND %r,[%ir] AND %r,[%ir]+ AND [%ir],%r AND [%ir]+,%r AND [%ir],imm4 AND [%ir]+,imm4 BIT %r,imm4 %r,[%ir]+ [%ir],%r [%ir]+,%r BIT [%ir],imm4 BIT [%ir]+,imm4 CALR [addr6] CALR sign8 CALZ imm8 CLR [addr6],imm2 CMP %r,%r’ CMP %r,imm4 CMP %r,[%ir] CMP %r,[%ir]+ CMP [%ir],%r CMP [%ir]+,%r CMP [%ir],imm4 CMP [%ir]+,imm4 CMP %ir,imm8 DEC [addr6] DEC [ir],n4 DEC [ir]+,n4 DEC %sp EX %A,%B EX %r,[%ir] EX %r,[%ir]+ HALT INC [addr6] INC [ir],n4 INC [ir]+,n4 INC %sp INT imm6 JP %Y JR %A JR %BA JR [addr6] JR sign8 JRC sign8 JRNC sign8 JRNZ sign8 JRZ sign8 LD %r,%r’ LD %r,imm4 LD %r,[%ir] LD %r,[%ir]+ LD [%ir],%r LD [%ir]+,%r LD [%ir],imm4 LD [%ir]+,imm4 LD [%ir],[%ir’] LD [%ir],[%ir’]+ LD [%ir]+,[%ir’] LD [%ir]+,[%ir’]+ LDB %BA,imm8 LDB %BA,[%ir]+ LDB %BA,%EXT LDB %BA,%rr LDB %BA,%sp LDB [%ir]+,%BA LDB [%X]+,imm8 LDB %EXT,imm8 LDB %EXT,%BA LDB %rr,imm8 LDB %rr,%BA LDB %sp,%BA NOP OR %r,%r’ OR %r,imm4 OR %F,imm4 OR %r,[%ir] OR %r,[%ir]+ OR [%ir],%r OR [%ir]+,%r OR [%ir],imm4 OR [%ir]+,imm4 POP %r POP %ir PUSH %r PUSH %ir RET RETD imm8 RETI RETS RL %r RL [%ir] RL [%ir]+ RR %r RR [%ir] RR [%ir]+ SBC %r,%r SBC %r,imm4 SBC %r,[%ir] SBC %r,[%ir]+ SBC [%ir],%r SBC [%ir]+,%r SBC [%ir],imm4 SBC [%ir]+,imm4 SBC %B,%A,n4 SBC %B,[%ir],n4 SBC %B,[%ir]+,n4 SBC [%ir],%B,n4 SBC [%ir]+,%B,n4 SBC [%ir],0,n4 SBC [%ir]+,0,n4 SET [addr6],imm2 SLL %r SLL [%ir] SLL [%ir]+ SLP SRL %r SRL [%ir] SRL [%ir]+ SUB %r,%r’ SUB %r,imm4 SUB %r,[%ir] SUB %r,[%ir]+ SUB [%ir],%r SUB [%ir]+,%r SUB [%ir],imm4 SUB [%ir]+,imm4 TST [addr6],imm2 XOR %r,%r’ XOR %r,imm4 XOR %F,imm4 XOR %r,[%ir] XOR %r,[%ir]+ XOR [%ir],%r XOR [%ir]+,%r XOR [%ir],imm4 XOR [%ir]+,imm4 Index AMERICA EUROPE ASIA In pursuit of “Saving” Technology, Epson electronic devices “Saving” Technology Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams Epson IS energy savings Core CPU Manual