Epson S1C63000 SUB [%ir],imm4, SUB [%ir]+,imm4, 2 cycles, Subtract immediate data imm4 from location [ir reg.]

CHAPTER 4: INSTRUCTION SET

SUB [%ir],imm4

Subtract immediate data imm4 from location [ir reg.]

2 cycles

Function: [ir] ←

[ir] - imm4

Subtracts the 4-bit immediate data imm4 from the data memory addressed by the ir register (X

or Y).

Code:

Mnemonic

MSB

LSB

SUB [%X],imm4

1

1

0

0

0

0

0

0

0

i3

i2

i1

i0

1800H–180FH

SUB [%Y],imm4

1

1

0

0

0

0

0

1

0

i3

i2

i1

i0

1820H–182FH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Valid

Extended

LDB

%EXT,imm8

operation: SUB

[%X],imm4

[00imm8] ←

[00imm8] - imm4 (00imm8 = 0000H + 00H to FFH)

LDB

%EXT,imm8

SUB

[%Y],imm4

[FFimm8] ←

[FFimm8] - imm4 (FFimm8 = FF00H + 00H to FFH)

SUB [%ir]+,imm4

Subtract immediate data imm4 from location [ir reg.] and increment ir reg. 2 cycles

Function: [ir] ←

[ir] - imm4, ir ←

ir + 1

Subtracts the 4-bit immediate data imm4 from the data memory addressed by the ir register (X

or Y). Then increments the ir register (X or Y). The flags change due to the operation result of

the data memory and the increment result of the ir register does not affect the flags.

Code:

Mnemonic

MSB

LSB

SUB [%X]+,imm4

1

1

0

0

0

0

0

0

1

i3

i2

i1

i0

1810H–181FH

SUB [%Y]+,imm4

1

1

0

0

0

0

0

1

1

i3

i2

i1

i0

1830H–183FH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Invalid

138 EPSON S1C63000 CORE CPU MANUAL