CHAPTER 4: INSTRUCTION SET

 

Mnemonic

 

 

 

 

Machine code

 

 

 

Operation

Cycle

 

Flag

 

EXT.

Page

 

12

11

10

9

 

8

7

6

5

4

3

2

1

0

E

I

C

Z

mode

LDB

%BA,%YH

1

1

1

1

1

1

1

0

0

1

0

1

1

BA YH

1

– –

107

 

%BA,%YL

1

1

1

1

1

1

1

0

0

1

0

1

0

BA YL

1

– –

107

 

%BA,imm8

0

1

0

0

1

i7 i6 i5 i4

i3 i2 i1 i0

BA imm8

1

105

 

%BA,[%X]+

1

1

1

1

1

1

1

0

1

1

0

0

0

A [X], B [X+1], X X+2

2

– –

106

 

%BA,[%Y]+

1

1

1

1

1

1

1

0

1

1

0

1

0

A [Y], B [Y+1], Y Y+2

2

– –

106

 

%EXT,%BA

1

1

1

1

1

1

1

0

1

0

1

0

X

EXT BA

1

– –

109

 

%EXT,imm8

0

1

0

0

0

i7 i6 i5 i4

i3 i2 i1 i0

EXT imm8

1

109

 

%SP1,%BA

1

1

1

1

1

1

1

0

0

0

1

0

X

SP1 BA

1

– –

111

 

%SP2,%BA

1

1

1

1

1

1

1

0

0

0

1

1

X

SP2 BA

1

– –

111

 

%XH,%BA

1

1

1

1

1

1

1

0

0

0

0

0

1

XH BA

1

– –

110

 

%XL,%BA

1

1

1

1

1

1

1

0

0

0

0

0

0

XL BA

1

– –

110

 

%XL,imm8

0

1

0

1

0

i7 i6 i5 i4

i3 i2 i1 i0

XL imm8

1

110

 

%YH,%BA

1

1

1

1

1

1

1

0

0

0

0

1

1

YH BA

1

– –

110

 

%YL,%BA

1

1

1

1

1

1

1

0

0

0

0

1

0

YL BA

1

– –

110

 

%YL,imm8

0

1

0

1

1

i7 i6 i5 i4

i3 i2 i1 i0

YL imm8

1

110

 

[%X]+,%BA

1

1

1

1

1

1

1

0

1

1

0

0

1

[X] A, [X+1] B, X X+2

2

– –

108

 

[%X]+,imm8

0

0

0

0

1

i7 i6 i5 i4

i3 i2 i1 i0

[X] i3~0, [X+1] i7~4, X X+2

2

108

 

[%Y]+,%BA

1

1

1

1

1

1

1

0

1

1

0

1

1

[Y] A, [Y+1] B, Y Y+2

2

– –

108

NOP

 

1

1

1

1

1

1

1

1

1

1

1

1

X

No operation (PC PC+1)

1

– –

111

OR

%A,%A

1

1

0

1

1

0

1

1

1

0

0

0

X

A AA

1

112

 

%A,%B

1

1

0

1

1

0

1

1

1

0

0

1

X

A AB

1

112

 

%A,imm4

1

1

0

1

1

0

1

0

0

i3 i2 i1 i0

A Aimm4

1

112

 

%A,[%X]

1

1

0

1

1

0

1

1

0

0

0

0

0

A A[X]

1

113

 

%A,[%X]+

1

1

0

1

1

0

1

1

0

0

0

0

1

A A[X], X X+1

1

114

 

%A,[%Y]

1

1

0

1

1

0

1

1

0

0

0

1

0

A A[Y]

1

113

 

%A,[%Y]+

1

1

0

1

1

0

1

1

0

0

0

1

1

A A[Y], Y Y+1

1

114

 

%B,%A

1

1

0

1

1

0

1

1

1

0

1

0

X

B BA

1

112

 

%B,%B

1

1

0

1

1

0

1

1

1

0

1

1

X

B BB

1

112

 

%B,imm4

1

1

0

1

1

0

1

0

1

i3 i2 i1 i0

B Bimm4

1

112

 

%B,[%X]

1

1

0

1

1

0

1

1

0

0

1

0

0

B B[X]

1

113

 

%B,[%X]+

1

1

0

1

1

0

1

1

0

0

1

0

1

B B[X], X X+1

1

114

 

%B,[%Y]

1

1

0

1

1

0

1

1

0

0

1

1

0

B B[Y]

1

113

 

%B,[%Y]+

1

1

0

1

1

0

1

1

0

0

1

1

1

B B[Y], Y Y+1

1

114

 

%F,imm4

1

0

0

0

0

1

0

0

1

i3 i2 i1 i0

F Fimm4

1

↑ ↑ ↑ ↑

113

 

[%X],%A

1

1

0

1

1

0

1

1

0

1

0

0

0

[X] [X]A

2

114

 

[%X],%B

1

1

0

1

1

0

1

1

0

1

1

0

0

[X] [X]B

2

114

 

[%X],imm4

1

1

0

1

1

0

0

0

0

i3 i2 i1 i0

[X] [X]imm4

2

115

 

[%X]+,%A

1

1

0

1

1

0

1

1

0

1

0

0

1

[X] [X]A, X X+1

2

115

 

[%X]+,%B

1

1

0

1

1

0

1

1

0

1

1

0

1

[X] [X]B, X X+1

2

115

 

[%X]+,imm4

1

1

0

1

1

0

0

0

1

i3 i2 i1 i0

[X] [X]imm4, X X+1

2

116

 

[%Y],%A

1

1

0

1

1

0

1

1

0

1

0

1

0

[Y] [Y]A

2

114

 

[%Y],%B

1

1

0

1

1

0

1

1

0

1

1

1

0

[Y] [Y]B

2

114

 

[%Y],imm4

1

1

0

1

1

0

0

1

0

i3 i2 i1 i0

[Y] [Y]imm4

2

115

 

[%Y]+,%A

1

1

0

1

1

0

1

1

0

1

0

1

1

[Y] [Y]A, Y Y+1

2

115

 

[%Y]+,%B

1

1

0

1

1

0

1

1

0

1

1

1

1

[Y] [Y]B, Y Y+1

2

115

 

[%Y]+,imm4

1

1

0

1

1

0

0

1

1

i3 i2 i1 i0

[Y] [Y]imm4, Y Y+1

2

116

POP

%A

1

1

1

1

1

1

1

1

0

1

1

1

1

A [SP2], SP2 SP2+1

1

– –

116

 

%B

1

1

1

1

1

1

1

1

0

1

1

1

0

B [SP2], SP2 SP2+1

1

– –

116

 

%F

1

1

1

1

1

1

1

1

0

1

1

0

1

F [SP2], SP2 SP2+1

1

↔ ↔ ↔ ↔

116

 

%X

1

1

1

1

1

1

1

1

0

1

0

0

1

X ([SP14+3]~[SP14]), SP1 SP1+1

1

– –

117

 

%Y

1

1

1

1

1

1

1

1

0

1

0

1

X

Y ([SP14+3]~[SP14]), SP1 SP1+1

1

– –

117

PUSH

%A

1

1

1

1

1

1

1

1

0

0

1

1

1

[SP2-1] A, SP2 SP2-1

1

– –

117

 

%B

1

1

1

1

1

1

1

1

0

0

1

1

0

[SP2-1] B, SP2 SP2-1

1

– –

117

 

%F

1

1

1

1

1

1

1

1

0

0

1

0

1

[SP2-1] F, SP2 SP2-1

1

– –

117

 

%X

1

1

1

1

1

1

1

1

0

0

0

0

1

([(SP1-1)4+3]~[(SP1-1)4]) X, SP1 SP1-1

1

118

 

%Y

1

1

1

1

1

1

1

1

0

0

0

1

X

([(SP1-1)4+3]~[(SP1-1)4]) Y, SP1 SP1-1

1

118

RET

 

1

1

1

1

1

1

1

1

1

1

0

X 0

PC ([SP14+3]~[SP14]), SP1 SP1+1

1

– –

118

RETD

imm8

1

0

0

0

1

i7 i6 i5 i4

i3 i2 i1 i0

PC ([SP14+3]~[SP14]), SP1 SP1+1

3

119

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[X] i3~0, [X+1] i7~4, X X+2

 

 

 

 

 

 

 

52

EPSON

S1C63000 CORE CPU MANUAL