Epson S1C63000 I/O, I/O, I/O, NMI, IRQ, Type, USLP, IACK, NACK, STOP, BS16, DBS0, DBS1, DBS1, DBS0, D0–D3, FETCH, State, signal, signal, I00–I12, M00–M15, is low), Function

CHAPTER 1: OUTLINE

Table 1.4.1(b) Input/output signal list (2)

Type

Terminal name

I/O

Function

Data bus

I00–I12

I

Instruction bus

Inputs an instruction code.

M00–M15

I/O

16-bit data bus

A bidirectional data bus to connect to the RAM (stack RAM) for 16-bit accessing.

D0–D3

I/O

4-bit data bus

A bidirectional data bus to connect to the RAM and I/O.

Bus control

O

Data read

RD

signal

Goes to a low level when the CPU reads data (from RAM, I/O).

O

Data write

WR

Goes to a low level when the CPU writes data (to RAM, I/O).

O

Read interrupt vector

RDIV

Goes to a low level when the CPU reads an interrupt vector.

System control

I

Reset input

SR

signal

A low level input resets the CPU.

O

Micro sleep

USLP

Goes to a low level when the CPU executes the SLP instruction.

The peripheral circuit stops oscillation on the basis of this signal.

Interrupt signal

I

Non-maskable interrupt request

NMI

An interrupt request terminal for an interrupt that cannot be masked by software.

It is accepted at the falling edge of an input signal to this terminal.

I

Interrupt request

IRQ

An interrupt request terminal for interrupts that can be masked by software.

It is accepted by a low level signal input to this terminal.

O

Interrupt acknowledge

IACK

Goes to a low level while executing an

or

interrupt response cycle.

NMI

IRQ

O

Non-maskable interrupt acknowledge

NACK

Goes to a low level while executing a non-maskable interrupt response cycle.

Status signal

O

Fetch cycle

FETCH

Goes to a low level when the CPU fetches an instruction.

O

Stop signal

STOP

Goes to a low level when the CPU is in stop status after executing the HALT

or SLP instruction, or in reset status

is low).

(SR

IF

O

Interrupt flag

Outputs a status (inverted value) of the interrupt flag in the flag (F) register.

BS16

O

16-bit access

Goes to a low level when the CPU accesses to a 16-bit RAM.

DBS0

O

Data bus status

DBS1

Outputs data bus status (for both the 4-bit and 16-bit data bus).

DBS1

DBS0

State

0

0

High impedance

0

1

Interrupt vector read

1

0

Memory write

1

1

Memory read

See Chapter 3, "CPU OPERATION", for the timing of the signals.

S1C63000 CORE CPU MANUAL EPSON 3