Epson S1C63000 CHAPTER 2 ARCHITECTURE, 2.1 ALU and Registers, 2.1.1 ALU, 2.1.2 Register configuration

CHAPTER 2: ARCHITECTURE

CHAPTER 2 ARCHITECTURE

This chapter explains the S1C63000 ALU, registers, configuration of the program memory area and data memory area, and addressing.

2.1 ALU and Registers

2.1.1 ALU

The ALU (Arithmetic and Logic Unit) loads 4-bit data from a memory or a register and operates the data according to the instruction. Table 2.1.1.1 shows the ALU operation functions.

Table 2.1.1.1 ALU operation functions

Function classification	Mnemonic	Operation
Arithmetic	ADD	Addition
	ADC	Addition with carry
	SUB	Subtraction
	SBC	Subtraction with carry
	CMP	Comparison
	INC	Increment (adds 1)
	DEC	Decrement (subtracts 1)
Logic	AND	Logical product
	OR	Logical sum
	XOR	Exclusive OR
	BIT	Bit test
	CLR	Bit clear
	SET	Bit set
	TST	Bit test
Rotate / shift	RL	Rotate to left with carry
	RR	Rotate to right with carry
	SLL	Logical shift to left
	SRL	Logical shift to right

The operation result is stored to a register or memory according to the instruction.

In addition, the Z (zero) flag and C (carry) flag are set/reset according to the operation result.

2.1.2 Register configuration

Figure 2.1.2.1 shows the register configuration of the S1C63000.

	15							PC						0	Program counter
	15							X						0	Index register X
	7			XH				0	7	XL				0
	15							Y						0	Index register Y
	7			YH				0	7	YL				0
	15						QUEUE							0	Queue register
	0	0	0	0	0	0	7		SP1			0	0	0	Stack pointer 1
				00H					7	SP2				0	Stack pointer 2
									7	EXT				0	Extension register
									7	BA				0	Data register B & A
									3 B	0	3	A		0
											3	F		0	Flag register
Fig. 2.1.2.1 Register configuration											E	I	C	Z

4 EPSON S1C63000 CORE CPU MANUAL