CHAPTER 4: INSTRUCTION SET
ALU logic operation (2/2)
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| Machine code |
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| Operation | Cycle |
| Flag | EXT. | Page | ||||||||
| 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | E | I | C | Z | mode | ||||
XOR | %A,%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | X | A ← A∀A | 1 | ↓ | – | – ↑ | ⋅ | 139 | ||
| %A,%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | X | A ← A∀B | 1 | ↓ | – | ⋅ | 139 | |||
| %A,imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | i3 i2 i1 i0 | A ← A∀imm4 | 1 | ↓ | – | ⋅ | 140 | ||||||
| %A,[%X] | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | A ← A∀[X] | 1 | ↓ | – | ● | 141 | |||
| %A,[%X]+ | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | A ← A∀[X], X ← X+1 | 1 | ↓ | – | ⋅ | 141 | |||
| %A,[%Y] | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | A ← A∀[Y] | 1 | ↓ | – | ● | 141 | |||
| %A,[%Y]+ | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | A ← A∀[Y], Y ← Y+1 | 1 | ↓ | – | ⋅ | 141 | |||
XOR | %B,%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | X | B ← B∀A | 1 | ↓ | – | ⋅ | 139 | |||
| %B,%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | X | B ← B∀B | 1 | ↓ | – | – ↑ | ⋅ | 139 | ||
| %B,imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | i3 i2 i1 i0 | B ← B∀imm4 | 1 | ↓ | – | ⋅ | 140 | ||||||
| %B,[%X] | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | B ← B∀[X] | 1 | ↓ | – | ● | 141 | |||
| %B,[%X]+ | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | B ← B∀[X], X ← X+1 | 1 | ↓ | – | ⋅ | 141 | |||
| %B,[%Y] | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | B ← B∀[Y] | 1 | ↓ | – | ● | 141 | |||
| %B,[%Y]+ | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | B ← B∀[Y], Y ← Y+1 | 1 | ↓ | – | ⋅ | 141 | |||
XOR | %F,imm4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | i3 i2 i1 i0 | F ← F∀imm4 | 1 | ↔ ↔ ↔ ↔ | ⋅ | 140 | |||||||
XOR | [%X],%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | [X] ← [X]∀A | 2 | ↓ – | ● | 142 | ||||
| [%X],%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | [X] ← [X]∀B | 2 | ↓ – | ● | 142 | ||||
| [%X],imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | i3 i2 i1 i0 | [X] ← [X]∀imm4 | 2 | ↓ – | ● | 143 | |||||||
| [%X]+,%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | [X] ← [X]∀A, X ← X+1 | 2 | ↓ – | ⋅ | 142 | ||||
| [%X]+,%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | [X] ← [X]∀B, X ← X+1 | 2 | ↓ – | ⋅ | 142 | ||||
| [%X]+,imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | i3 i2 i1 i0 | [X] ← [X]∀imm4, X ← X+1 | 2 | ↓ – | ⋅ | 143 | |||||||
XOR | [%Y],%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | [Y] ← [Y]∀A | 2 | ↓ – | ● | 142 | ||||
| [%Y],%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | [Y] ← [Y]∀B | 2 | ↓ – | ● | 142 | ||||
| [%Y],imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | i3 i2 i1 i0 | [Y] ← [Y]∀imm4 | 2 | ↓ – | ● | 143 | |||||||
| [%Y]+,%A | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | [Y] ← [Y]∀A, Y ← Y+1 | 2 | ↓ – | ⋅ | 142 | ||||
| [%Y]+,%B | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | [Y] ← [Y]∀B, Y ← Y+1 | 2 | ↓ – | ⋅ | 142 | ||||
| [%Y]+,imm4 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | i3 i2 i1 i0 | [Y] ← [Y]∀imm4, Y ← Y+1 | 2 | ↓ – | ⋅ | 143 | |||||||
BIT | %A,%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | X | A∧A | 1 | ↓ – | ⋅ | 78 | ||||
| %A,%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | X | A∧B | 1 | ↓ – | ⋅ | 78 | ||||
| %A,imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | i3 i2 i1 i0 | A∧imm4 | 1 | ↓ – | ⋅ | 78 | |||||||
| %A,[%X] | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | A∧[X] | 1 | ↓ – | ● | 79 | ||||
| %A,[%X]+ | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | A∧[X], X ← X+1 | 1 | ↓ – | ⋅ | 79 | ||||
| %A,[%Y] | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | A∧[Y] | 1 | ↓ – | ● | 79 | ||||
| %A,[%Y]+ | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | A∧[Y], Y ← Y+1 | 1 | ↓ – | ⋅ | 79 | ||||
BIT | %B,%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | X | B∧A | 1 | ↓ – | ⋅ | 78 | ||||
| %B,%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | X | B∧B | 1 | ↓ – | ⋅ | 78 | ||||
| %B,imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | i3 i2 i1 i0 | B∧imm4 | 1 | ↓ – | ⋅ | 78 | |||||||
| %B,[%X] | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | B∧[X] | 1 | ↓ – | ● | 79 | ||||
| %B,[%X]+ | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | B∧[X], X ← X+1 | 1 | ↓ – | ⋅ | 79 | ||||
| %B,[%Y] | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | B∧[Y] | 1 | ↓ – | ● | 79 | ||||
| %B,[%Y]+ | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | B∧[Y], Y ← Y+1 | 1 | ↓ – | ⋅ | 79 | ||||
BIT | [%X],%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | [X]∧A | 1 | ↓ – | ● | 80 | ||||
| [%X],%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | [X]∧B | 1 | ↓ – | ● | 80 | ||||
| [%X],imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | i3 i2 i1 i0 | [X]∧imm4 | 1 | ↓ – | ● | 81 | |||||||
| [%X]+,%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | [X]∧A, X ← X+1 | 1 | ↓ – | ⋅ | 80 | ||||
| [%X]+,%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | [X]∧B, X ← X+1 | 1 | ↓ – | ⋅ | 80 | ||||
| [%X]+,imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | i3 i2 i1 i0 | [X]∧imm4, X ← X+1 | 1 | ↓ – | ⋅ | 81 | |||||||
BIT | [%Y],%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | [Y]∧A | 1 | ↓ – | ● | 80 | ||||
| [%Y],%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | [Y]∧B | 1 | ↓ – | ● | 80 | ||||
| [%Y],imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | i3 i2 i1 i0 | [Y]∧imm4 | 1 | ↓ – | ● | 81 | |||||||
| [%Y]+,%A | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | [Y]∧A, Y ← Y+1 | 1 | ↓ – | ⋅ | 80 | ||||
| [%Y]+,%B | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | [Y]∧B, Y ← Y+1 | 1 | ↓ – | ⋅ | 80 | ||||
| [%Y]+,imm4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | i3 i2 i1 i0 | [Y]∧imm4, Y ← Y+1 | 1 | ↓ – | ⋅ | 81 | |||||||
CLR | [00addr6],imm2 | 1 | 0 | 1 | 0 | 0 | i1 i0 a5 a4 | a3 a2 a1 a0 | [00addr6] ← [00addr6]∧not (2imm2) | 2 | ↓ – | ⋅ | 83 | ||||||||||
| [FFaddr6],imm2 | 1 | 0 | 1 | 0 | 1 | i1 i0 a5 a4 | a3 a2 a1 a0 | [FFaddr6] ← [FFaddr6]∧not (2imm2) | 2 | ↓ – | ⋅ | 83 | ||||||||||
SET | [00addr6],imm2 | 1 | 0 | 1 | 1 | 0 | i1 i0 a5 a4 | a3 a2 a1 a0 | [00addr6] ← [00addr6]∧(2imm2) | 2 | ↓ – | ⋅ | 131 | ||||||||||
| [FFaddr6],imm2 | 1 | 0 | 1 | 1 | 1 | i1 i0 a5 a4 | a3 a2 a1 a0 | [FFaddr6] ← [FFaddr6]∧(2imm2) | 2 | ↓ – | ⋅ | 131 | ||||||||||
TST | [00addr6],imm2 | 1 | 0 | 0 | 1 | 0 | i1 i0 a5 a4 | a3 a2 a1 a0 | [00addr6]∧(2imm2) | 1 | ↓ – | ⋅ | 139 | ||||||||||
| [FFaddr6],imm2 | 1 | 0 | 0 | 1 | 1 | i1 i0 a5 a4 | a3 a2 a1 a0 | [FFaddr6]∧(2imm2) | 1 | ↓ – | ⋅ | 139 | ||||||||||
S1C63000 CORE CPU MANUAL | EPSON | 45 |