Epson S1C63000 AND [%ir],%r, AND [%ir]+,%r, 2 cycles, Logical AND of r reg. and location [ir reg.]

CHAPTER 4: INSTRUCTION SET

AND [%ir],%r				Logical AND of r reg. and location [ir reg.]																2 cycles
Function: [ir] ←		[ir] ∧ r
	Performs a logical AND operation of the content of the r register (A or B) and the content of the
	data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:	Mnemonic			MSB															LSB
	AND [%X],%A				1		1	0	1	0	0	1	1		0	1	0	0	0	1A68H
	AND [%X],%B				1		1	0	1	0	0	1	1		0	1	1	0	0	1A6CH
	AND [%Y],%A				1		1	0	1	0	0	1	1		0	1	0	1	0	1A6AH
	AND [%Y],%B				1		1	0	1	0	0	1	1		0	1	1	1	0	1A6EH
Flags:	E		I	C		Z
	↓		–	–		↕
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Valid
Extended	LDB		%EXT,imm8
operation: AND		[%X],%r			[00imm8] ←					[00imm8] ∧			r (00imm8 = 0000H + 00H to FFH)
	LDB		%EXT,imm8
	AND	[%Y],%r			[FFimm8] ←					[FFimm8] ∧				r (FFimm8 = FF00H + 00H to FFH)

AND [%ir]+,%r					Logical AND of r reg. and location [ir reg.] and increment ir reg. 2 cycles
Function: [ir] ←		[ir] ∧		r, ir ←		ir + 1
	Performs a logical AND operation of the content of the r register (A or B) and the content of the
	data memory addressed by the ir register (X or Y), and stores the result in that address. Then
	increments the ir register (X or Y). The flags change due to the operation result of the data
	memory and the increment result of the ir register does not affect the flags.
Code:	Mnemonic					MSB													LSB
	AND [%X]+,%A						1	1	0	1	0	0	1	1	0	1	0	0		1	1A69H
	AND [%X]+,%B						1	1	0	1	0	0	1	1	0	1	1	0		1	1A6DH
	AND [%Y]+,%A						1	1	0	1	0	0	1	1	0	1	0	1		1	1A6BH
	AND [%Y]+,%B						1	1	0	1	0	0	1	1	0	1	1	1		1	1A6FH
Flags:	E		I		C		Z
	↓		–		–		↕
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Invalid

76 EPSON S1C63000 CORE CPU MANUAL