Epson S1C63000 manual 56

CHAPTER 4: INSTRUCTION SET

	Mnemonic					Machine code										Operation	Cycle		Flag			EXT.	Page
		12	11	10	9		8	7	6	5	4	3	2	1	0			E	I	C	Z	mode
BIT	[%Y],imm4	1	1	0	1	0		1	0	1	0	i3 i2 i1 i0				[Y]∧imm4	1	↓ –		–↔		●	81
	[%Y]+,%A	1	1	0	1	0		1	1	1	0	1	0	1	1	[Y]∧A, Y ← Y+1	1	↓ – –↔				⋅	80
	[%Y]+,%B	1	1	0	1	0		1	1	1	0	1	1	1	1	[Y]∧B, Y ← Y+1	1	↓ – –↔				⋅	80
	[%Y]+,imm4	1	1	0	1	0		1	0	1	1	i3 i2 i1 i0				[Y]∧imm4, Y ← Y+1	1	↓ –		–↔		⋅	81
CALR	[00addr6]	1	1	1	1	1		0	0 a5 a4			a3 a2 a1 a0				([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,	2	↓ –		–	–	⋅	82
																SP1 ← SP1-1, PC ← PC+[00addr6]+1
CALR	sign8	0	0	0	1	0		s7 s6 s5 s4				s3 s2 s1 s0				([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,	1	↓ –		–	–	●	82
																SP1 ← SP1-1, PC ← PC+sign8+1 (sign8=-128~127)
CALZ	imm8	0	0	0	1	1		i7 i6 i5 i4				i3 i2 i1 i0				([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,	1	↓ –		–	–	⋅	83
																SP1 ← SP1-1, PC ← imm8
CLR	[00addr6],imm2	1	0	1	0	0		i1 i0 a5 a4				a3 a2 a1 a0				[00addr6] ← [00addr6]∧not (2imm2)	2	↓ –		–↔		⋅	83
	[FFaddr6],imm2	1	0	1	0	1		i1 i0 a5 a4				a3 a2 a1 a0				[FFaddr6] ← [FFaddr6]∧not (2imm2)	2	↓ –		–↔		⋅	83
CMP	%A,%A	1	1	1	1	0		0	1	1	1	X 0		0 0		A-A	1	↓ – ↓ ↑				⋅	84
	%A,%B	1	1	1	1	0		0	1	1	1	X 0		1 0		A-B	1	↓ –↔ ↔				⋅	84
	%A,imm4	1	1	1	1	0		0	1	0	0	i3 i2 i1 i0				A-imm4	1	↓ –↔ ↔				⋅	84
	%A,[%X]	1	1	1	1	0		0	1	1	0	0	0	0	0	A-[X]	1	↓ –↔ ↔				●	85
	%A,[%X]+	1	1	1	1	0		0	1	1	0	0	0	0	1	A-[X], X ← X+1	1	↓ –↔ ↔				⋅	85
	%A,[%Y]	1	1	1	1	0		0	1	1	0	0	0	1	0	A-[Y]	1	↓ –↔ ↔				●	85
	%A,[%Y]+	1	1	1	1	0		0	1	1	0	0	0	1	1	A-[Y], Y ← Y+1	1	↓ –↔ ↔				⋅	85
	%B,%A	1	1	1	1	0		0	1	1	1	X 1		0 0		B-A	1	↓ –↔ ↔				⋅	84
	%B,%B	1	1	1	1	0		0	1	1	1	X 1		1 0		B-B	1	↓ – ↓ ↑				⋅	84
	%B,imm4	1	1	1	1	0		0	1	0	1	i3 i2 i1 i0				B-imm4	1	↓ –↔ ↔				⋅	84
	%B,[%X]	1	1	1	1	0		0	1	1	0	0	1	0	0	B-[X]	1	↓ –↔ ↔				●	85
	%B,[%X]+	1	1	1	1	0		0	1	1	0	0	1	0	1	B-[X], X ← X+1	1	↓ –↔ ↔				⋅	85
	%B,[%Y]	1	1	1	1	0		0	1	1	0	0	1	1	0	B-[Y]	1	↓ –↔ ↔				●	85
	%B,[%Y]+	1	1	1	1	0		0	1	1	0	0	1	1	1	B-[Y], Y ← Y+1	1	↓ –↔ ↔				⋅	85
	%X,imm8	0	1	1	1	0		[	FFH - imm8						]	X-imm8 (imm8=0~255)	1	↓ –↔ ↔				●	88
	%Y,imm8	0	1	1	1	1		[	FFH - imm8						]	Y-imm8 (imm8=0~255)	1	↓ –↔ ↔				●	88
	[%X],%A	1	1	1	1	0		0	1	1	0	1	0	0	0	[X]-A	1	↓ –↔ ↔				●	86
	[%X],%B	1	1	1	1	0		0	1	1	0	1	1	0	0	[X]-B	1	↓ –↔ ↔				●	86
	[%X],imm4	1	1	1	1	0		0	0	0	0	i3 i2 i1 i0				[X]-imm4	1	↓ –↔ ↔				●	87
	[%X]+,%A	1	1	1	1	0		0	1	1	0	1	0	0	1	[X]-A, X ← X+1	1	↓ –↔ ↔				⋅	86
	[%X]+,%B	1	1	1	1	0		0	1	1	0	1	1	0	1	[X]-B, X ← X+1	1	↓ –↔ ↔				⋅	86
	[%X]+,imm4	1	1	1	1	0		0	0	0	1	i3 i2 i1 i0				[X]-imm4, X ← X+1	1	↓ –↔ ↔				⋅	87
	[%Y],%A	1	1	1	1	0		0	1	1	0	1	0	1	0	[Y]-A	1	↓ –↔ ↔				●	86
	[%Y],%B	1	1	1	1	0		0	1	1	0	1	1	1	0	[Y]-B	1	↓ –↔ ↔				●	86
	[%Y],imm4	1	1	1	1	0		0	0	1	0	i3 i2 i1 i0				[Y]-imm4	1	↓ –↔ ↔				●	87
	[%Y]+,%A	1	1	1	1	0		0	1	1	0	1	0	1	1	[Y]-A, Y ← Y+1	1	↓ –↔ ↔				⋅	86
	[%Y]+,%B	1	1	1	1	0		0	1	1	0	1	1	1	1	[Y]-B, Y ← Y+1	1	↓ –↔ ↔				⋅	86
	[%Y]+,imm4	1	1	1	1	0		0	0	1	1	i3 i2 i1 i0				[Y]-imm4, Y ← Y+1	1	↓ –↔ ↔				⋅	87
DEC	%SP1	1	1	1	1	1		1	1	1	0	0	0	0	0	SP1 ← SP1-1	1	↓ – –↔				⋅	90
	%SP2	1	1	1	1	1		1	1	1	0	0	1	0	0	SP2 ← SP2-1	1	↓ – –↔				⋅	90
	[%X],n4	1	1	1	0	0		1	0	0	0	n3 n2 n1 n0				[X] ← N's adjust ([X]-1)	2	↓ –↔ ↔				●	89
	[%X]+,n4	1	1	1	0	0		1	0	0	1	n3 n2 n1 n0				[X] ← N's adjust ([X]-1), X← X+1	2	↓ –↔ ↔				⋅	89
	[%Y],n4	1	1	1	0	0		1	0	1	0	n3 n2 n1 n0				[Y] ← N's adjust ([Y]-1)	2	↓ –↔ ↔				●	89
	[%Y]+,n4	1	1	1	0	0		1	0	1	1	n3 n2 n1 n0				[Y] ← N's adjust ([Y]-1), Y← Y+1	2	↓ –↔ ↔				⋅	89
	[00addr6]	1	0	0	0	0		0	0 a5 a4			a3 a2 a1 a0				[00addr6] ← [00addr6]-1	2	↓ –↔ ↔				⋅	88
EX	%A,%B	1	1	1	1	1		1	1	1	1	0	1	1	1	A ↔ B	1	↓ – – –				⋅	90
	%A,[%X]	1	0	0	0	0		1	1	1	1	1	0	0	0	A ↔ [X]	2	↓ – – –				●	91
	%A,[%X]+	1	0	0	0	0		1	1	1	1	1	0	0	1	A ↔ [X], X ← X+1	2	↓ – – –				⋅	91
	%A,[%Y]	1	0	0	0	0		1	1	1	1	1	0	1	0	A ↔ [Y]	2	↓ – – –				●	91
	%A,[%Y]+	1	0	0	0	0		1	1	1	1	1	0	1	1	A ↔ [Y], Y ← Y+1	2	↓ – – –				⋅	91
	%B,[%X]	1	0	0	0	0		1	1	1	1	1	1	0	0	B ↔ [X]	2	↓ – – –				●	91
	%B,[%X]+	1	0	0	0	0		1	1	1	1	1	1	0	1	B ↔ [X], X ← X+1	2	↓ – – –				⋅	91
	%B,[%Y]	1	0	0	0	0		1	1	1	1	1	1	1	0	B ↔ [Y]	2	↓ – – –				●	91
	%B,[%Y]+	1	0	0	0	0		1	1	1	1	1	1	1	1	B ↔ [Y], Y ← Y+1	2	↓ – – –				⋅	91
HALT		1	1	1	1	1		1	1	1	1	1	1	0	0	Halt	2	↓ – – –				⋅	92
INC	%SP1	1	1	1	1	1		1	1	1	0	1	0	0	0	SP1 ← SP1+1	1	↓ – –↔				⋅	94
	%SP2	1	1	1	1	1		1	1	1	0	1	1	0	0	SP2 ← SP2+1	1	↓ – –↔				⋅	94

50 EPSON S1C63000 CORE CPU MANUAL