Epson S1C63000 ADC [%ir],imm4, ADC [%ir]+,imm4, 2 cycles, Add with carry immediate data imm4 to location [ir reg.], LDB, ADC, LDB, ADC, ir +, [ir] ←, [ir] ←, %EXT,imm8

CHAPTER 4: INSTRUCTION SET

ADC [%ir],imm4

Add with carry immediate data imm4 to location [ir reg.]

2 cycles

Function: [ir] ←

[ir] + imm4 + C

Adds the 4-bit immediate data imm4 and carry (C) to the data memory addressed by the ir

register (X or Y).

Code:

Mnemonic

MSB

LSB

ADC [%X],imm4

1

1

0

0

1

1

0

0

0

i3

i2

i1

i0

1980H–198FH

ADC [%Y],imm4

1

1

0

0

1

1

0

1

0

i3

i2

i1

i0

19A0H–19AFH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Valid

Extended

LDB

%EXT,imm8

operation: ADC

[%X],imm4

[00imm8] ←

[00imm8] + imm4 + C (00imm8 = 0000H + 00H to FFH)

LDB

%EXT,imm8

ADC

[%Y],imm4

[FFimm8] ←

[FFimm8] + imm4 + C (FFimm8 = FF00H + 00H to FFH)

ADC [%ir]+,imm4

Add with carry immediate data imm4 to location [ir reg.] and increment ir reg. 2 cycles

Function: [ir] ←

[ir] + imm4 + C, ir ←

ir + 1

Adds the immediate data imm4 and carry (C) to the data memory addressed by the ir register

(X or Y). Then increments the ir register (X or Y). The flags change due to the operation result

of the data memory and the increment result of the ir register does not affect the flags.

Code:

Mnemonic

MSB

LSB

ADC [%X]+,imm4

1

1

0

0

1

1

0

0

1

i3

i2

i1

i0

1990H–199FH

ADC [%Y]+,imm4

1

1

0

0

1

1

0

1

1

i3

i2

i1

i0

19B0H–19BFH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Invalid

64 EPSON S1C63000 CORE CPU MANUAL