CHAPTER 4: INSTRUCTION SET

4.2.3 Instruction list by function

4-bit data transfer

 

Mnemonic

 

 

 

 

Machine code

 

 

 

Operation

Cycle

 

Flag

 

EXT.

Page

 

12

11

10

9

 

8

7

6

5

4

3

2

1

0

E

I

C

Z

mode

LD

%A,%A

1

1

1

1

0

1

1

1

1

0

0

0

0

A A

1

– – –

99

 

%A,%B

1

1

1

1

0

1

1

1

1

0

0

1

0

A B

1

– – –

99

 

%A,%F

1

1

1

1

1

1

1

1

1

0

1

1

0

A F

1

– – –

99

 

%A,imm4

1

1

1

1

0

1

1

0

0

i3 i2 i1 i0

A imm4

1

– – –

100

 

%A,[%X]

1

1

1

1

0

1

1

1

0

0

0

0

0

A [X]

1

– – –

100

 

%A,[%X]+

1

1

1

1

0

1

1

1

0

0

0

0

1

A [X], X X+1

1

– – –

101

 

%A,[%Y]

1

1

1

1

0

1

1

1

0

0

0

1

0

A [Y]

1

– – –

100

 

%A,[%Y]+

1

1

1

1

0

1

1

1

0

0

0

1

1

A [Y], Y Y+1

1

– – –

101

LD

%B,%A

1

1

1

1

0

1

1

1

1

0

1

0

0

B A

1

– – –

99

 

%B,%B

1

1

1

1

0

1

1

1

1

0

1

1

0

B B

1

– – –

99

 

%B,imm4

1

1

1

1

0

1

1

0

1

i3 i2 i1 i0

B imm4

1

– – –

100

 

%B,[%X]

1

1

1

1

0

1

1

1

0

0

1

0

0

B [X]

1

– – –

100

 

%B,[%X]+

1

1

1

1

0

1

1

1

0

0

1

0

1

B [X], X X+1

1

– – –

101

 

%B,[%Y]

1

1

1

1

0

1

1

1

0

0

1

1

0

B [Y]

1

– – –

100

 

%B,[%Y]+

1

1

1

1

0

1

1

1

0

0

1

1

1

B [Y], Y Y+1

1

– – –

101

LD

%F,%A

1

1

1

1

1

1

1

1

1

0

1

0

1

F A

1

↔ ↔ ↔ ↔

99

 

%F,imm4

1

0

0

0

0

1

0

1

1

i3 i2 i1 i0

F imm4

1

↔ ↔ ↔ ↔

100

LD

[%X],%A

1

1

1

1

0

1

1

1

0

1

0

0

0

[X] A

1

– – –

101

 

[%X],%B

1

1

1

1

0

1

1

1

0

1

1

0

0

[X] B

1

– – –

101

 

[%X],imm4

1

1

1

1

0

1

0

0

0

i3 i2 i1 i0

[X] imm4

1

102

 

[%X],[%Y]

1

1

1

1

0

1

1

1

1

1

0

1

0

[X] [Y]

2

103

 

[%X],[%Y]+

1

1

1

1

0

1

1

1

1

1

0

1

1

[X] [Y], Y Y+1

2

104

 

[%X]+,%A

1

1

1

1

0

1

1

1

0

1

0

0

1

[X] A, X X+1

1

– – –

102

 

[%X]+,%B

1

1

1

1

0

1

1

1

0

1

1

0

1

[X] B, X X+1

1

– – –

102

 

[%X]+,imm4

1

1

1

1

0

1

0

0

1

i3 i2 i1 i0

[X] imm4, X X+1

1

103

 

[%X]+,[%Y]

1

1

1

1

0

1

1

1

1

1

1

1

0

[X] [Y], X X+1

2

104

 

[%X]+,[%Y]+

1

1

1

1

0

1

1

1

1

1

1

1

1

[X] [Y], X X+1, Y Y+1

2

105

LD

[%Y],%A

1

1

1

1

0

1

1

1

0

1

0

1

0

[Y] A

1

– – –

101

 

[%Y],%B

1

1

1

1

0

1

1

1

0

1

1

1

0

[Y] B

1

– – –

101

 

[%Y],imm4

1

1

1

1

0

1

0

1

0

i3 i2 i1 i0

[Y] imm4

1

102

 

[%Y],[%X]

1

1

1

1

0

1

1

1

1

1

0

0

0

[Y] [X]

2

103

 

[%Y],[%X]+

1

1

1

1

0

1

1

1

1

1

0

0

1

[Y] [X], X X+1

2

104

 

[%Y]+,%A

1

1

1

1

0

1

1

1

0

1

0

1

1

[Y] A, Y Y+1

1

– – –

102

 

[%Y]+,%B

1

1

1

1

0

1

1

1

0

1

1

1

1

[Y] B, Y Y+1

1

– – –

102

 

[%Y]+,imm4

1

1

1

1

0

1

0

1

1

i3 i2 i1 i0

[Y] imm4, Y Y+1

1

103

 

[%Y]+,[%X]

1

1

1

1

0

1

1

1

1

1

1

0

0

[Y] [X], Y Y+1

2

104

 

[%Y]+,[%X]+

1

1

1

1

0

1

1

1

1

1

1

0

1

[Y] [X], Y Y+1, X X+1

2

105

EX

%A,%B

1

1

1

1

1

1

1

1

1

0

1

1

1

A B

1

– – –

90

EX

%A,[%X]

1

0

0

0

0

1

1

1

1

1

0

0

0

A [X]

2

– – –

91

 

%A,[%X]+

1

0

0

0

0

1

1

1

1

1

0

0

1

A [X], X X+1

2

– – –

91

 

%A,[%Y]

1

0

0

0

0

1

1

1

1

1

0

1

0

A [Y]

2

– – –

91

 

%A,[%Y]+

1

0

0

0

0

1

1

1

1

1

0

1

1

A [Y], Y Y+1

2

– – –

91

EX

%B,[%X]

1

0

0

0

0

1

1

1

1

1

1

0

0

B [X]

2

– – –

91

 

%B,[%X]+

1

0

0

0

0

1

1

1

1

1

1

0

1

B [X], X X+1

2

– – –

91

 

%B,[%Y]

1

0

0

0

0

1

1

1

1

1

1

1

0

B [Y]

2

– – –

91

 

%B,[%Y]+

1

0

0

0

0

1

1

1

1

1

1

1

1

B [Y], Y Y+1

2

– – –

91

40

EPSON

S1C63000 CORE CPU MANUAL