Epson S1C63000 SBC [%ir]+,imm4, SBC %B,%A,n4, 2 cycles, SBC %B,%A,n4 Subtract with carry A reg. from B reg. in specified radix, ir +, [ir] ←, 1890H–189FH, 18B0H–18BFH

CHAPTER 4: INSTRUCTION SET

SBC [%ir]+,imm4

Subtract with carry immediate data imm4 from location [ir reg.] and increment ir reg. 2 cycles

Function: [ir] ←

[ir] - imm4 - C, ir ←

ir + 1

Subtracts the immediate data imm4 and carry (C) from the data memory addressed by the ir

register (X or Y). Then increments the ir register (X or Y). The flags change due to the operation

result of the data memory and the increment result of the ir register does not affect the flags.

Code:

Mnemonic

MSB

LSB

SBC [%X]+,imm4

1

1

0

0

0

1

0

0

1

i3

i2

i1

i0

1890H–189FH

SBC [%Y]+,imm4

1

1

0

0

0

1

0

1

1

i3

i2

i1

i0

18B0H–18BFH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Immediate data

Dst: Register indirect

Extended addressing: Invalid

SBC %B,%A,n4 Subtract with carry A reg. from B reg. in specified radix 2 cycles

Function: B ← N’s adjust (B - A - C)

Subtracts the content of the A register and carry (C) from the B register. The operation result is adjusted with n4 as the radix. The C flag is set according to the radix.

Code:

Mnemonic

MSB

LSB

SBC %B,%A,n4

1

0

0

0

0

1

1

0

0

n3

n2

n1

n0

10C0H–10CFH

Flags:

E

I

C

Z

↓

–

↕

↕

Mode:

Src: Register direct

Dst: Register direct

Extended addressing: Invalid

Note: n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B.

S1C63000 CORE CPU MANUAL EPSON 127