Epson S1C63000 XOR [%ir],%r, XOR [%ir]+,%r, 2 cycles, 2 cycles, Exclusive OR r reg. and location [ir reg.], Exclusive OR r reg. and location [ir reg.] and increment ir reg

CHAPTER 4: INSTRUCTION SET

XOR [%ir],%r				Exclusive OR r reg. and location [ir reg.]																	2 cycles
Function: [ir] ←		[ir] ∀ r
	Performs an exclusive OR operation of the content of the r register (A or B) and the content of
	the data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:	Mnemonic			MSB															LSB
	XOR [%X],%A				1		1	0	1	1	1	1	1		0	1	0	0		0	1BE8H
	XOR [%X],%B				1		1	0	1	1	1	1	1		0	1	1	0		0	1BECH
	XOR [%Y],%A				1		1	0	1	1	1	1	1		0	1	0	1		0	1BEAH
	XOR [%Y],%B				1		1	0	1	1	1	1	1		0	1	1	1		0	1BEEH
Flags:	E		I	C		Z
	↓		–	–		↕
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Valid
Extended	LDB		%EXT,imm8
operation: XOR		[%X],%r			[00imm8] ←					[00imm8] ∀				r (00imm8 = 0000H + 00H to FFH)
	LDB		%EXT,imm8
	XOR		[%Y],%r		[FFimm8] ←					[FFimm8] ∀				r (FFimm8 = FF00H + 00H to FFH)

XOR [%ir]+,%r					Exclusive OR r reg. and location [ir reg.] and increment ir reg.																	2 cycles
Function: [ir] ←		[ir] ∀		r, ir ←		ir + 1
	Performs an exclusive OR operation of the content of the r register (A or B) and the content of
	the data memory addressed by the ir register (X or Y), and stores the result in that address.
	Then increments the ir register (X or Y). The flags change due to the operation result of the data
	memory and the increment result of the ir register does not affect the flags.
Code:	Mnemonic					MSB													LSB
	XOR [%X]+,%A						1	1	0	1	1	1	1	1	0	1	0	0		1	1BE9H
	XOR [%X]+,%B						1	1	0	1	1	1	1	1	0	1	1	0		1	1BEDH
	XOR [%Y]+,%A						1	1	0	1	1	1	1	1	0	1	0	1		1	1BEBH
	XOR [%Y]+,%B						1	1	0	1	1	1	1	1	0	1	1	1		1	1BEFH
Flags:	E		I		C		Z
	↓		–		–		↕
Mode:	Src: Register direct
	Dst: Register indirect
	Extended addressing: Invalid

142 EPSON S1C63000 CORE CPU MANUAL