Epson S1C63000 1.3 Block Diagram, 1.4 Input-OutputSignals

CHAPTER 1: OUTLINE

1.3 Block Diagram

Figure 1.3.1 shows the S1C63000 block diagram.

IA00 –IA15 RD WR RDIV BS16 DBS0 DBS1 CLK SR PK PL STOP USLP IRQ NMI IACK NACK FETCH VDD VSS I00 –I12

BUS

TIMING & INTERRUPT

POWER

IR (13)

CONTROL

CONTROL

SUPPLY

PC (16)

INSTRUCTION

DECODER

∝ Instruction

QUEUE (16)

X (16)

A (4)

B (4)

Y (16)

SP2 (8)

Port A

Port B

EXT (8)

4-bit ALU

SP1 (8)

ADDRESS

OPERATOR

Port

A

Port B

16-bit

ADDER

F (4)

DATA ADDRESS LATCH

S1C63000

M00 –M15

DA00 –DA15

IF

D0 –D3

Fig. 1.3.1 S1C63000 block diagram

1.4 Input-Output Signals

Tables 1.4.1 (a) and 1.4.1 (b) show the input/output signals between the S1C63000 and peripheral circuits.

Table 1.4.1(a) Input/output signal list (1)

Type	Terminal name	I/O			Function
Power supply	VDD (VD1)	I	Power supply (+)
			Inputs a plus supply voltage.
	VSS (VS1)	I	Power supply (-)
			Inputs a minus supply voltage.
Clock	CLK	I	Clock input
			Inputs the system clock from the peripheral circuit.
	PK	O	2-phase divided clock output
	PL		Outputs the 2-phase divided signals to be generated from the system clock
			input to the CLK terminal as following phase.
			CLK
			PK
			PL
				1 cycle
Address bus	IA00–IA15	O	Instruction address output
			Outputs an instruction (code ROM) address.
	DA00–DA15	O	Data address output
			Outputs a data (RAM, I/O) address.

2 EPSON S1C63000 CORE CPU MANUAL