CHAPTER 3: CPU OPERATION

3. Instructions that set the stack pointer

LDB %SP1,%BA

LDB %SP2,%BA

These two instructions are also accepted after fetching the next instruction. However, these instructions must be executed as a pair. When one of them is fetched at first, all the interrupts including NMI are masked (interrupts cannot be accepted). Then, when the other instruction is fetched, that mask is released and interrupts can be accepted after the next instruction is fetched.

 

 

0

1

2

3

4

5

CLK

 

 

 

 

 

 

 

PK

 

 

 

 

 

 

 

PL

 

 

 

 

 

 

 

PC

pc-2

pc-1

 

pc

 

0100H

ANY

FETCH

ANY

ANY

DUMMY

 

(0100H)

ANY

BS16

 

 

 

 

 

 

 

DBS1/0

 

ANY

 

2

1

2

ANY

WR

 

 

 

 

 

 

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

DUMMY

 

 

RDIV

 

 

 

 

 

 

 

DA00–DA15

 

ANY

 

SP2-1

DUMMY

SP1-1

 

D0–D3

 

 

 

F reg.

ANY

 

 

M00–M15

 

 

 

 

 

pc

 

NMI

 

 

 

 

 

 

 

IACK

 

 

 

 

 

 

 

NACK

 

 

 

 

 

 

 

IF

 

 

 

 

 

 

 

Interrupt sampling

 

Interrupt processing by the hardware

Executing the interrupt service routine

 

 

 

 

4–6 cycle

 

 

 

 

 

0

 

1

2

3

4

5

CLK

 

 

 

 

 

 

 

 

PK

 

 

 

 

 

 

 

 

PL

 

 

 

 

 

 

 

 

PC

pc-3

pc-2

pc-1

 

pc

 

0100H

ANY

FETCH

ANY

LDB %EXT,imm8

LD %A,[%X]

DUMMY

 

 

(0100H)

ANY

BS16

 

 

 

 

 

 

 

 

DBS1/0

 

ANY

0

3

2

1

2

ANY

WR

 

 

 

 

 

 

 

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DUMMY

 

 

RDIV

 

 

 

 

 

 

 

 

DA00–DA15

 

ANY

 

00xxH

SP2-1

DUMMY

SP1-1

 

D0–D3

 

 

 

[00xxH]

F reg.

ANY

 

 

M00–M15

 

 

 

 

 

 

pc

 

NMI

IACK

NACK

Fig. 3.5.2.1 NMI sequence (normal acceptance)

In this chart, the dummy fetch cycle starts after fetching the "LD %A, [%X]" instruction that follows the "LDB %EXT, imm8" instruction.

Fig. 3.5.2.2 NMI sequence

IF

Interrupt sampling

 

 

 

 

 

 

 

 

Interrupt processing by the hardware

Executing the interrupt service routine

 

(interrupt acceptance after 1 instruction)

28

EPSON

S1C63000 CORE CPU MANUAL