CHAPTER 4: INSTRUCTION SET

Stack operation

 

Mnemonic

 

 

 

 

Machine code

 

 

 

 

Operation

Cycle

 

Flag

 

EXT.

Page

 

12

11

10

9

 

8

7

6

5

4

 

3

2

1

0

E

I

C

Z

mode

 

 

 

 

 

 

 

PUSH

%A

1

1

1

1

1

1

1

1

0

 

0

1

1

1

[SP2-1] ← A, SP2 ← SP2-1

1

↓ – – –

⋅

117

 

%B

1

1

1

1

1

1

1

1

0

 

0

1

1

0

[SP2-1] ← B, SP2 ← SP2-1

1

↓ – – –

⋅

117

 

%F

1

1

1

1

1

1

1

1

0

 

0

1

0

1

[SP2-1] ← F, SP2 ← SP2-1

1

↓ – – –

⋅

117

 

%X

1

1

1

1

1

1

1

1

0

 

0

0

0

1

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← X, SP1 ← SP1-1

1

↓ –

–

–

⋅

118

 

%Y

1

1

1

1

1

1

1

1

0

 

0

0

1

X

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← Y, SP1 ← SP1-1

1

↓ –

–

–

⋅

118

POP

%A

1

1

1

1

1

1

1

1

0

 

1

1

1

1

A ← [SP2], SP2 ← SP2+1

1

↓ – – –

⋅

116

 

%B

1

1

1

1

1

1

1

1

0

 

1

1

1

0

B ← [SP2], SP2 ← SP2+1

1

↓ – – –

⋅

116

 

%F

1

1

1

1

1

1

1

1

0

 

1

1

0

1

F ← [SP2], SP2 ← SP2+1

1

↔ ↔ ↔ ↔

⋅

116

 

%X

1

1

1

1

1

1

1

1

0

 

1

0

0

1

X ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

1

↓ – – –

⋅

117

 

%Y

1

1

1

1

1

1

1

1

0

 

1

0

1

X

Y ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

1

↓ – – –

⋅

117

Branch control

 

Mnemonic

 

 

 

 

Machine code

Operation

Cycle

 

Flag

 

EXT.

Page

 

12

11

10

9

 

8

7

6

5

4

 

3

2

1

0

E

I

C

Z

mode

JR

sign8

0

0

0

0

0

s7 s6 s5 s4

 

s3 s2 s1 s0

PC ← PC+sign8+1 (sign8=-128~127)

1

↓ –

–

–

●

97

JR

%A

1

1

1

1

1

1

1

1 1

 

0 0 0 1

PC ← PC+A+1

1

↓ – – –

⋅

95

 

%BA

1

1

1

1

1

1

1

1 1

 

0 0 0 0

PC ← PC+BA+1

1

↓ – – –

⋅

96

JR

[00addr6]

1

1

1

1

1

0

1 a5 a4

 

a3 a2 a1 a0

PC ← PC+[00addr6]+1

2

↓ –

–

–

⋅

96

JRC

sign8

0

0

1

0

0

s7 s6 s5 s4

 

s3 s2 s1 s0

If C=1 then PC ← PC+sign8+1 (sign8=-128~127)

1

↓ –

–

–

●

97

JRNC

sign8

0

0

1

0

1

s7 s6 s5 s4

 

s3 s2 s1 s0

If C=0 then PC ← PC+sign8+1 (sign8=-128~127)

1

↓ –

–

–

●

98

JRZ

sign8

0

0

1

1

0

s7 s6 s5 s4

 

s3 s2 s1 s0

If Z=1 then PC ← PC+sign8+1 (sign8=-128~127)

1

↓ –

–

–

●

99

JRNZ

sign8

0

0

1

1

1

s7 s6 s5 s4

 

s3 s2 s1 s0

If Z=0 then PC ← PC+sign8+1 (sign8=-128~127)

1

↓ –

–

–

●

98

JP

%Y

1

1 1 1 1

1 1 1 1

 

 

0 0 1 X

PC ← Y

1

↓ – – –

⋅

95

CALZ

imm8

0

0

0

1

1

i7 i6 i5 i4

 

i3 i2 i1 i0

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,

1

↓ –

–

–

⋅

83

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1 ← SP1-1, PC ← imm8

 

 

 

 

 

 

 

CALR

sign8

0

0

0

1

0

s7 s6 s5 s4

 

s3 s2 s1 s0

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,

1

↓ –

–

–

●

82

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1 ← SP1-1, PC ← PC+sign8+1 (sign8=-128~127)

 

 

 

 

 

 

 

CALR

[00addr6]

1

1

1

1

1

0

0 a5 a4

 

a3 a2 a1 a0

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,

2

↓ –

–

–

⋅

82

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1 ← SP1-1, PC ← PC+[00addr6]+1

 

 

 

 

 

 

 

INT

imm6

1

1

1

1

1

1

0

i5 i4

 

i3 i2 i1 i0

[SP2-1] ← F, SP2 ← SP2-1

3

↓ –

–

–

⋅

94

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

([(SP1-1)∗4+3]~[(SP1-1)∗4]) ← PC+1,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1 ← SP1-1, PC ← imm6 (imm6=0100H~013FH)

 

 

 

 

 

 

 

RET

 

1

1

1

1

1

1

1

1 1

 

 

1 0 X 0

PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

1

↓ – – –

⋅

118

RETS

 

1

1

1

1

1

1

1

1 1

 

1 0 1 1

PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

2

↓ – – –

⋅

120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC ← PC+1

 

 

 

 

 

 

 

RETD

imm8

1

0

0

0

1

i7 i6 i5 i4

 

i3 i2 i1 i0

PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

3

↓ –

–

–

⋅

119

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[X] ← i3~0, [X+1] ← i7~4, X ← X+2

 

 

 

 

 

 

 

RETI

 

1

1

1

1

1

1

1

1 1

 

1 0 0 1

PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1

2

↔ ↔ ↔ ↔

⋅

119

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F ← [SP2], SP2 ← SP2+1

 

 

 

 

 

 

 

System control

Mnemonic

 

 

 

 

Machine code

 

 

 

 

Operation

Cycle

 

Flag

EXT.

Page

12

11

10

9

 

8

7

6

5

4

 

3

2

1

0

E

I

C

Z

mode

HALT

 

1

1

1

1

1

1

1

1

1

 

1

1

0

0

Halt

2

↓ – – –

⋅

92

SLP

 

1

1

1

1

1

1

1

1

1

 

1

1

0

1

Sleep

2

↓ – –

–

⋅

133

NOP

 

1

1

1

1

1

1

1

1

1

 

1

1

1

X

No operation (PC ← PC+1)

1

↓ – –

–

⋅

111

Note: • The extended addressing (combined with the E flag) is available only for the instructions indicated with ● in the EXT. mode row. Operation of other instructions (indicated with ⋅) cannot be guaranteed, therefore do not write data to the EXT register or do not set the E flag immediately before those instructions.

•X in the machine code row indicates that the bit is valid even though it is "0" or "1", but the assembler generates it as "0". When entering the code directly, such as for debugging, "0" should be entered.

S1C63000 CORE CPU MANUAL

EPSON

47